pp_off           2067 drivers/gpu/drm/gma500/cdv_intel_dp.c                 u32 pp_on, pp_off, pp_div;
pp_off           2081 drivers/gpu/drm/gma500/cdv_intel_dp.c                 pp_off = REG_READ(PP_OFF_DELAYS);
pp_off           2091 drivers/gpu/drm/gma500/cdv_intel_dp.c                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
pp_off           2094 drivers/gpu/drm/gma500/cdv_intel_dp.c                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
pp_off           1017 drivers/gpu/drm/i915/display/intel_dp.c 	i915_reg_t pp_off;
pp_off           1037 drivers/gpu/drm/i915/display/intel_dp.c 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
pp_off           6381 drivers/gpu/drm/i915/display/intel_dp.c 	u32 pp_on, pp_off, pp_ctl;
pp_off           6393 drivers/gpu/drm/i915/display/intel_dp.c 	pp_off = I915_READ(regs.pp_off);
pp_off           6398 drivers/gpu/drm/i915/display/intel_dp.c 	seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
pp_off           6399 drivers/gpu/drm/i915/display/intel_dp.c 	seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
pp_off           6533 drivers/gpu/drm/i915/display/intel_dp.c 	u32 pp_on, pp_off, port_sel = 0;
pp_off           6570 drivers/gpu/drm/i915/display/intel_dp.c 	pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
pp_off           6597 drivers/gpu/drm/i915/display/intel_dp.c 	I915_WRITE(regs.pp_off, pp_off);
pp_off           6617 drivers/gpu/drm/i915/display/intel_dp.c 		      I915_READ(regs.pp_off),