pp_id             840 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 	TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id),
pp_id             841 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 	TP_ARGS(id, enc_id, pp_id),
pp_id             845 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		__field(	uint32_t,		pp_id	)
pp_id             850 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		__entry->pp_id = pp_id;
pp_id             853 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		  __entry->enc_id, __entry->pp_id)
pp_id              47 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	int pp_id = mixer->pp;
pp_id              73 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg);
pp_id              75 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 		REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), 0xfff0);
pp_id              77 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 		REG_MDP5_PP_VSYNC_INIT_VAL(pp_id), mode->vdisplay);
pp_id              78 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1);
pp_id              79 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay);
pp_id              80 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id),
pp_id              91 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	int pp_id = mixer->pp;
pp_id             108 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 1);
pp_id             117 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	int pp_id = mixer->pp;
pp_id             119 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 0);