pp_div 2067 drivers/gpu/drm/gma500/cdv_intel_dp.c u32 pp_on, pp_off, pp_div; pp_div 2082 drivers/gpu/drm/gma500/cdv_intel_dp.c pp_div = REG_READ(PP_DIVISOR); pp_div 2097 drivers/gpu/drm/gma500/cdv_intel_dp.c cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> pp_div 1018 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_div; pp_div 1041 drivers/gpu/drm/i915/display/intel_dp.c regs->pp_div = INVALID_MMIO_REG; pp_div 1043 drivers/gpu/drm/i915/display/intel_dp.c regs->pp_div = PP_DIVISOR(pps_idx); pp_div 1083 drivers/gpu/drm/i915/display/intel_dp.c u32 pp_div; pp_div 1087 drivers/gpu/drm/i915/display/intel_dp.c pp_div = I915_READ(pp_div_reg); pp_div 1088 drivers/gpu/drm/i915/display/intel_dp.c pp_div &= PP_REFERENCE_DIVIDER_MASK; pp_div 1091 drivers/gpu/drm/i915/display/intel_dp.c I915_WRITE(pp_div_reg, pp_div | 0x1F); pp_div 6401 drivers/gpu/drm/i915/display/intel_dp.c if (i915_mmio_reg_valid(regs.pp_div)) { pp_div 6402 drivers/gpu/drm/i915/display/intel_dp.c u32 pp_div; pp_div 6404 drivers/gpu/drm/i915/display/intel_dp.c pp_div = I915_READ(regs.pp_div); pp_div 6406 drivers/gpu/drm/i915/display/intel_dp.c seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; pp_div 6602 drivers/gpu/drm/i915/display/intel_dp.c if (i915_mmio_reg_valid(regs.pp_div)) { pp_div 6603 drivers/gpu/drm/i915/display/intel_dp.c I915_WRITE(regs.pp_div, pp_div 6618 drivers/gpu/drm/i915/display/intel_dp.c i915_mmio_reg_valid(regs.pp_div) ? pp_div 6619 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(regs.pp_div) :