pp_display_cfg 40 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c const struct dm_pp_display_configuration *pp_display_cfg) pp_display_cfg 52 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->cpu_cc6_disable; pp_display_cfg 55 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->cpu_pstate_disable; pp_display_cfg 58 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->cpu_pstate_separation_time; pp_display_cfg 61 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->nb_pstate_switch_disable; pp_display_cfg 64 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->display_count; pp_display_cfg 66 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->display_count; pp_display_cfg 69 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->min_engine_clock_khz/10; pp_display_cfg 71 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->min_engine_clock_deep_sleep_khz/10; pp_display_cfg 73 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->min_memory_clock_khz/10; pp_display_cfg 76 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->min_engine_clock_deep_sleep_khz/10; pp_display_cfg 78 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->min_dcfclock_khz/10; pp_display_cfg 81 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->all_displays_in_sync; pp_display_cfg 83 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->avail_mclk_switch_time_us; pp_display_cfg 86 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->disp_clk_khz/10; pp_display_cfg 89 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->avail_mclk_switch_time_in_disp_active_us; pp_display_cfg 91 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index; pp_display_cfg 93 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_display_cfg->line_time_in_us; pp_display_cfg 95 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh; pp_display_cfg 99 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c for (i = 0; i < pp_display_cfg->display_count; i++) { pp_display_cfg 101 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c &pp_display_cfg->disp_configs[i]; pp_display_cfg 385 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; pp_display_cfg 387 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); pp_display_cfg 389 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c dce110_fill_display_configs(context, pp_display_cfg); pp_display_cfg 391 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) pp_display_cfg 392 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); pp_display_cfg 121 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c struct dm_pp_display_configuration *pp_display_cfg) pp_display_cfg 131 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c &pp_display_cfg->disp_configs[num_cfgs]; pp_display_cfg 169 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->display_count = num_cfgs; pp_display_cfg 176 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; pp_display_cfg 182 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->all_displays_in_sync = pp_display_cfg 184 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->nb_pstate_switch_disable = pp_display_cfg 186 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->cpu_cc6_disable = pp_display_cfg 188 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->cpu_pstate_disable = pp_display_cfg 190 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->cpu_pstate_separation_time = pp_display_cfg 199 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz, pp_display_cfg 204 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz pp_display_cfg 208 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( pp_display_cfg 219 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ? pp_display_cfg 220 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->min_engine_clock_khz : 0; pp_display_cfg 222 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->min_engine_clock_deep_sleep_khz pp_display_cfg 225 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->avail_mclk_switch_time_us = pp_display_cfg 228 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; pp_display_cfg 230 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; pp_display_cfg 232 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c dce110_fill_display_configs(context, pp_display_cfg); pp_display_cfg 235 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c if (pp_display_cfg->display_count == 1) { pp_display_cfg 239 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->crtc_index = pp_display_cfg 240 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->disp_configs[0].pipe_idx; pp_display_cfg 241 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; pp_display_cfg 244 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) pp_display_cfg 245 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); pp_display_cfg 35 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h struct dm_pp_display_configuration *pp_display_cfg); pp_display_cfg 493 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dm_pp_display_configuration *pp_display_cfg) pp_display_cfg 503 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c &pp_display_cfg->disp_configs[num_cfgs]; pp_display_cfg 541 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->display_count = num_cfgs; pp_display_cfg 598 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; pp_display_cfg 600 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); pp_display_cfg 602 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dce110_fill_display_configs(context, pp_display_cfg); pp_display_cfg 604 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) pp_display_cfg 605 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); pp_display_cfg 612 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; pp_display_cfg 614 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->all_displays_in_sync = pp_display_cfg 616 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->nb_pstate_switch_disable = pp_display_cfg 618 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->cpu_cc6_disable = pp_display_cfg 620 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->cpu_pstate_disable = pp_display_cfg 622 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->cpu_pstate_separation_time = pp_display_cfg 625 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz pp_display_cfg 628 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( pp_display_cfg 639 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4)? pp_display_cfg 640 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->min_engine_clock_khz : 0; pp_display_cfg 642 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->min_engine_clock_deep_sleep_khz pp_display_cfg 645 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->avail_mclk_switch_time_us = pp_display_cfg 648 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; pp_display_cfg 650 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; pp_display_cfg 652 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dce110_fill_display_configs(context, pp_display_cfg); pp_display_cfg 655 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (pp_display_cfg->display_count == 1) { pp_display_cfg 659 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->crtc_index = pp_display_cfg 660 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->disp_configs[0].pipe_idx; pp_display_cfg 661 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; pp_display_cfg 664 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) pp_display_cfg 665 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); pp_display_cfg 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h struct dm_pp_display_configuration *pp_display_cfg); pp_display_cfg 233 drivers/gpu/drm/amd/display/dc/dm_services.h const struct dm_pp_display_configuration *pp_display_cfg); pp_display_cfg 391 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct dm_pp_display_configuration pp_display_cfg;