pp_clks           251 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		const struct amd_pp_clocks *pp_clks,
pp_clks           257 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
pp_clks           260 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				pp_clks->count,
pp_clks           265 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		dc_clks->num_levels = pp_clks->count;
pp_clks           271 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
pp_clks           272 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
pp_clks           277 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		const struct pp_clock_levels_with_latency *pp_clks,
pp_clks           283 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
pp_clks           286 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				pp_clks->num_levels,
pp_clks           291 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->num_levels = pp_clks->num_levels;
pp_clks           297 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
pp_clks           298 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
pp_clks           299 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
pp_clks           304 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		const struct pp_clock_levels_with_voltage *pp_clks,
pp_clks           310 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
pp_clks           313 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				pp_clks->num_levels,
pp_clks           318 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->num_levels = pp_clks->num_levels;
pp_clks           324 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz,
pp_clks           325 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			 pp_clks->data[i].voltage_in_mv);
pp_clks           326 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
pp_clks           327 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
pp_clks           338 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct amd_pp_clocks pp_clks = { 0 };
pp_clks           344 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			dc_to_pp_clock_type(clk_type), &pp_clks)) {
pp_clks           352 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 					  &pp_clks)) {
pp_clks           358 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
pp_clks           424 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct pp_clock_levels_with_latency pp_clks = { 0 };
pp_clks           431 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 						&pp_clks);
pp_clks           437 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 						       &pp_clks))
pp_clks           442 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);