PcieLaneCount    1514 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
PcieLaneCount    1527 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
PcieLaneCount    3367 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 				lane_width = pptable->PcieLaneCount[i];
PcieLaneCount     404 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		pr_info("  .[%d] = %d\n", i, pptable->PcieLaneCount[i]);
PcieLaneCount     453 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h   uint8_t      PcieLaneCount[NUM_LINK_LEVELS];
PcieLaneCount     626 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h   uint8_t      PcieLaneCount[NUM_LINK_LEVELS];          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
PcieLaneCount     154 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     uint8_t     PcieLaneCount;          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
PcieLaneCount     145 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h 	uint8_t     PcieLaneCount;          /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
PcieLaneCount     130 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h     uint8_t     PcieLaneCount;          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 
PcieLaneCount     158 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h 	uint8_t     PcieLaneCount;
PcieLaneCount     168 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h 	uint8_t     PcieLaneCount;
PcieLaneCount     212 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     uint8_t     PcieLaneCount;
PcieLaneCount     237 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h   uint8_t     PcieLaneCount[NUM_LINK_LEVELS];          /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
PcieLaneCount     341 drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h   uint8_t      PcieLaneCount[NUM_LINK_LEVELS];
PcieLaneCount    1006 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->LinkLevel[i].PcieLaneCount =
PcieLaneCount     841 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
PcieLaneCount     775 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->LinkLevel[i].PcieLaneCount =
PcieLaneCount     779 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
PcieLaneCount     518 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->LinkLevel[i].PcieLaneCount =
PcieLaneCount     581 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
PcieLaneCount    1072 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					(pptable->PcieLaneCount[i] == 1) ? "x1" :
PcieLaneCount    1073 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					(pptable->PcieLaneCount[i] == 2) ? "x2" :
PcieLaneCount    1074 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					(pptable->PcieLaneCount[i] == 3) ? "x4" :
PcieLaneCount    1075 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					(pptable->PcieLaneCount[i] == 4) ? "x8" :
PcieLaneCount    1076 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					(pptable->PcieLaneCount[i] == 5) ? "x12" :
PcieLaneCount    1077 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					(pptable->PcieLaneCount[i] == 6) ? "x16" : "",
PcieLaneCount    1080 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					(lane_width == pptable->PcieLaneCount[i]) ?
PcieLaneCount    2636 drivers/gpu/drm/radeon/ci_dpm.c 		table->LinkLevel[i].PcieLaneCount =
PcieLaneCount     212 drivers/gpu/drm/radeon/smu7_discrete.h     uint8_t     PcieLaneCount;