postdiv2           73 arch/mips/ar7/clock.c 	u32 postdiv2;
postdiv2          262 arch/mips/ar7/clock.c 	int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
postdiv2          267 arch/mips/ar7/clock.c 		base, frequency, prediv, postdiv, postdiv2, mul);
postdiv2          284 arch/mips/ar7/clock.c 	writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
postdiv2          241 drivers/clk/pistachio/clk-pll.c 	     params->postdiv2 != old_postdiv2))
postdiv2          244 drivers/clk/pistachio/clk-pll.c 	if (params->postdiv2 > params->postdiv1)
postdiv2          254 drivers/clk/pistachio/clk-pll.c 		(params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);
postdiv2          273 drivers/clk/pistachio/clk-pll.c 	u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate;
postdiv2          282 drivers/clk/pistachio/clk-pll.c 	postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) &
postdiv2          293 drivers/clk/pistachio/clk-pll.c 	rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24);
postdiv2          387 drivers/clk/pistachio/clk-pll.c 	     params->postdiv2 != old_postdiv2))
postdiv2          390 drivers/clk/pistachio/clk-pll.c 	if (params->postdiv2 > params->postdiv1)
postdiv2          400 drivers/clk/pistachio/clk-pll.c 		(params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT);
postdiv2          413 drivers/clk/pistachio/clk-pll.c 	u32 val, prediv, fbdiv, postdiv1, postdiv2;
postdiv2          421 drivers/clk/pistachio/clk-pll.c 	postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) &
postdiv2          425 drivers/clk/pistachio/clk-pll.c 	rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2);
postdiv2          100 drivers/clk/pistachio/clk.h 	unsigned long long postdiv2;
postdiv2          142 drivers/clk/rockchip/clk-pll.c 	rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
postdiv2          173 drivers/clk/rockchip/clk-pll.c 	do_div(rate64, cur.postdiv2);
postdiv2          191 drivers/clk/rockchip/clk-pll.c 		rate->postdiv2, rate->dsmpd, rate->frac);
postdiv2          211 drivers/clk/rockchip/clk-pll.c 		       HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
postdiv2          307 drivers/clk/rockchip/clk-pll.c 		 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
postdiv2          310 drivers/clk/rockchip/clk-pll.c 		 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
postdiv2          314 drivers/clk/rockchip/clk-pll.c 		rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
postdiv2          617 drivers/clk/rockchip/clk-pll.c 	rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
postdiv2          650 drivers/clk/rockchip/clk-pll.c 	do_div(rate64, cur.postdiv2);
postdiv2          668 drivers/clk/rockchip/clk-pll.c 		rate->postdiv2, rate->dsmpd, rate->frac);
postdiv2          688 drivers/clk/rockchip/clk-pll.c 		       HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
postdiv2          786 drivers/clk/rockchip/clk-pll.c 		 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
postdiv2          789 drivers/clk/rockchip/clk-pll.c 		 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
postdiv2          793 drivers/clk/rockchip/clk-pll.c 		rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
postdiv2          205 drivers/clk/rockchip/clk.h 	.postdiv2 = _postdiv2,					\
postdiv2          254 drivers/clk/rockchip/clk.h 	unsigned int postdiv2;
postdiv2           54 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c 	u8 postdiv2;
postdiv2          345 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c 	cached_state->postdiv2 =
postdiv2          371 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c 			cached_state->postdiv2);