postdiv 361 arch/arm/mach-davinci/da850.c unsigned int postdiv; postdiv 370 arch/arm/mach-davinci/da850.c .postdiv = 1, postdiv 379 arch/arm/mach-davinci/da850.c .postdiv = 1, postdiv 388 arch/arm/mach-davinci/da850.c .postdiv = 1, postdiv 397 arch/arm/mach-davinci/da850.c .postdiv = 2, postdiv 406 arch/arm/mach-davinci/da850.c .postdiv = 3, postdiv 415 arch/arm/mach-davinci/da850.c .postdiv = 5, postdiv 267 arch/c6x/platforms/pll.c u32 ctrl, mult = 0, prediv = 0, postdiv = 0; postdiv 295 arch/c6x/platforms/pll.c postdiv = pll_read(pll, PLLPOST); postdiv 296 arch/c6x/platforms/pll.c if (postdiv & PLLDIV_EN) postdiv 297 arch/c6x/platforms/pll.c postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; postdiv 299 arch/c6x/platforms/pll.c postdiv = 1; postdiv 307 arch/c6x/platforms/pll.c if (postdiv) postdiv 308 arch/c6x/platforms/pll.c rate /= postdiv; postdiv 313 arch/c6x/platforms/pll.c prediv, mult, postdiv, rate / 1000000); postdiv 72 arch/mips/ar7/clock.c u32 postdiv; postdiv 99 arch/mips/ar7/clock.c int *postdiv, int *mul) postdiv 110 arch/mips/ar7/clock.c *postdiv = k; postdiv 115 arch/mips/ar7/clock.c static void calculate(int base, int target, int *prediv, int *postdiv, postdiv 124 arch/mips/ar7/clock.c *postdiv = tmp_base / tmp_gcd; postdiv 127 arch/mips/ar7/clock.c if ((*postdiv > 0) & (*postdiv <= 32)) postdiv 131 arch/mips/ar7/clock.c if (base / *prediv * *mul / *postdiv != target) { postdiv 132 arch/mips/ar7/clock.c approximate(base, target, prediv, postdiv, mul); postdiv 133 arch/mips/ar7/clock.c tmp_freq = base / *prediv * *mul / *postdiv; postdiv 140 arch/mips/ar7/clock.c *prediv, *postdiv, *mul); postdiv 167 arch/mips/ar7/clock.c int postdiv = (ctrl & POSTDIV_MASK) + 1; postdiv 168 arch/mips/ar7/clock.c int divisor = prediv * postdiv; postdiv 208 arch/mips/ar7/clock.c int prediv, postdiv, mul; postdiv 226 arch/mips/ar7/clock.c calculate(base_clock, frequency, &prediv, &postdiv, &mul); postdiv 228 arch/mips/ar7/clock.c writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl); postdiv 262 arch/mips/ar7/clock.c int prediv, int postdiv, int postdiv2, int mul, u32 frequency) postdiv 267 arch/mips/ar7/clock.c base, frequency, prediv, postdiv, postdiv2, mul); postdiv 276 arch/mips/ar7/clock.c writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv); postdiv 238 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; postdiv 309 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & postdiv 315 arch/mips/ath79/clock.c cpu_rate = cpu_pll / (postdiv + 1); postdiv 317 arch/mips/ath79/clock.c cpu_rate = ddr_pll / (postdiv + 1); postdiv 319 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & postdiv 325 arch/mips/ath79/clock.c ddr_rate = ddr_pll / (postdiv + 1); postdiv 327 arch/mips/ath79/clock.c ddr_rate = cpu_pll / (postdiv + 1); postdiv 329 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & postdiv 335 arch/mips/ath79/clock.c ahb_rate = ddr_pll / (postdiv + 1); postdiv 337 arch/mips/ath79/clock.c ahb_rate = cpu_pll / (postdiv + 1); postdiv 356 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; postdiv 398 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & postdiv 404 arch/mips/ath79/clock.c cpu_rate = cpu_pll / (postdiv + 1); postdiv 406 arch/mips/ath79/clock.c cpu_rate = ddr_pll / (postdiv + 1); postdiv 408 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & postdiv 414 arch/mips/ath79/clock.c ddr_rate = ddr_pll / (postdiv + 1); postdiv 416 arch/mips/ath79/clock.c ddr_rate = cpu_pll / (postdiv + 1); postdiv 418 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & postdiv 424 arch/mips/ath79/clock.c ahb_rate = ddr_pll / (postdiv + 1); postdiv 426 arch/mips/ath79/clock.c ahb_rate = cpu_pll / (postdiv + 1); postdiv 439 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; postdiv 481 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & postdiv 487 arch/mips/ath79/clock.c cpu_rate = ddr_pll / (postdiv + 1); postdiv 489 arch/mips/ath79/clock.c cpu_rate = cpu_pll / (postdiv + 1); postdiv 491 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & postdiv 497 arch/mips/ath79/clock.c ddr_rate = cpu_pll / (postdiv + 1); postdiv 499 arch/mips/ath79/clock.c ddr_rate = ddr_pll / (postdiv + 1); postdiv 501 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & postdiv 507 arch/mips/ath79/clock.c ahb_rate = ddr_pll / (postdiv + 1); postdiv 509 arch/mips/ath79/clock.c ahb_rate = cpu_pll / (postdiv + 1); postdiv 522 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; postdiv 583 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & postdiv 589 arch/mips/ath79/clock.c cpu_rate = ddr_pll / (postdiv + 1); postdiv 591 arch/mips/ath79/clock.c cpu_rate = cpu_pll / (postdiv + 1); postdiv 593 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & postdiv 599 arch/mips/ath79/clock.c ddr_rate = cpu_pll / (postdiv + 1); postdiv 601 arch/mips/ath79/clock.c ddr_rate = ddr_pll / (postdiv + 1); postdiv 603 arch/mips/ath79/clock.c postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & postdiv 609 arch/mips/ath79/clock.c ahb_rate = ddr_pll / (postdiv + 1); postdiv 611 arch/mips/ath79/clock.c ahb_rate = cpu_pll / (postdiv + 1); postdiv 52 drivers/clk/clk-axm5516.c unsigned long rate, fbdiv, refdiv, postdiv; postdiv 56 drivers/clk/clk-axm5516.c postdiv = ((control >> 0) & 0xf) + 1; postdiv 59 drivers/clk/clk-axm5516.c rate = (parent_rate / (refdiv * postdiv)) * fbdiv; postdiv 50 drivers/clk/imx/clk-composite-8m.c int *prediv, int *postdiv) postdiv 57 drivers/clk/imx/clk-composite-8m.c *postdiv = 1; postdiv 65 drivers/clk/imx/clk-composite-8m.c *postdiv = div2; postdiv 60 drivers/clk/keystone/pll.c u32 postdiv; postdiv 81 drivers/clk/keystone/pll.c u32 mult = 0, prediv, postdiv, val; postdiv 100 drivers/clk/keystone/pll.c postdiv = ((val & pll_data->clkod_mask) >> postdiv 103 drivers/clk/keystone/pll.c postdiv = readl(pll_data->pllod); postdiv 104 drivers/clk/keystone/pll.c postdiv = ((postdiv & pll_data->clkod_mask) >> postdiv 107 drivers/clk/keystone/pll.c postdiv = pll_data->postdiv; postdiv 111 drivers/clk/keystone/pll.c rate /= postdiv; postdiv 172 drivers/clk/keystone/pll.c if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { postdiv 63 drivers/clk/mediatek/clk-pll.c u32 pcw, int postdiv) postdiv 86 drivers/clk/mediatek/clk-pll.c return ((unsigned long)vco + postdiv - 1) / postdiv; postdiv 116 drivers/clk/mediatek/clk-pll.c int postdiv) postdiv 126 drivers/clk/mediatek/clk-pll.c val |= (ffs(postdiv) - 1) << pll->data->pd_shift; postdiv 159 drivers/clk/mediatek/clk-pll.c static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, postdiv 179 drivers/clk/mediatek/clk-pll.c *postdiv = 1 << val; postdiv 182 drivers/clk/mediatek/clk-pll.c *postdiv = 1 << val; postdiv 183 drivers/clk/mediatek/clk-pll.c if ((u64)freq * *postdiv >= fmin) postdiv 201 drivers/clk/mediatek/clk-pll.c u32 postdiv; postdiv 203 drivers/clk/mediatek/clk-pll.c mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); postdiv 204 drivers/clk/mediatek/clk-pll.c mtk_pll_set_rate_regs(pll, pcw, postdiv); postdiv 213 drivers/clk/mediatek/clk-pll.c u32 postdiv; postdiv 216 drivers/clk/mediatek/clk-pll.c postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; postdiv 217 drivers/clk/mediatek/clk-pll.c postdiv = 1 << postdiv; postdiv 222 drivers/clk/mediatek/clk-pll.c return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); postdiv 230 drivers/clk/mediatek/clk-pll.c int postdiv; postdiv 232 drivers/clk/mediatek/clk-pll.c mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate); postdiv 234 drivers/clk/mediatek/clk-pll.c return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv); postdiv 45 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint8_t postdiv; postdiv 44 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint8_t postdiv; /* divide by 2^n */ postdiv 811 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; postdiv 825 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; postdiv 826 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; postdiv 829 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; postdiv 881 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); postdiv 882 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; postdiv 889 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); postdiv 896 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); postdiv 897 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; postdiv 680 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->SclkFcwRangeTable[i].postdiv = postdiv 699 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; postdiv 701 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; postdiv 704 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; postdiv 757 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / postdiv 759 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; postdiv 767 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / postdiv 776 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / postdiv 778 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; postdiv 680 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); postdiv 681 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = postdiv->pll; postdiv 683 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u8 shift = postdiv->shift; postdiv 684 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u8 width = postdiv->width; postdiv 693 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c postdiv->flags, width); postdiv 700 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); postdiv 701 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = postdiv->pll; postdiv 706 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c postdiv->width, postdiv 707 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c postdiv->flags); postdiv 713 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); postdiv 714 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = postdiv->pll; postdiv 717 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u8 shift = postdiv->shift; postdiv 718 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u8 width = postdiv->width; postdiv 726 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c value = divider_get_val(rate, parent_rate, NULL, postdiv->width, postdiv 727 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c postdiv->flags); postdiv 342 drivers/gpu/drm/radeon/rv770_dpm.c static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv) postdiv 346 drivers/gpu/drm/radeon/rv770_dpm.c switch (postdiv) { postdiv 916 drivers/media/i2c/ov2659.c u32 prediv, postdiv, mult; postdiv 922 drivers/media/i2c/ov2659.c postdiv = ctrl1[i].div; postdiv 929 drivers/media/i2c/ov2659.c actual /= postdiv; postdiv 270 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c u8 postdiv; postdiv 917 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c if (cfg->postdiv == 1) { postdiv 921 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c int div = cfg->postdiv / 2 - 1; postdiv 1023 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c if (cfg->postdiv == 1) { postdiv 1028 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c v = (cfg->postdiv / 2) - 1; postdiv 238 drivers/video/fbdev/gxt4500.c int m, n, pdiv1, pdiv2, postdiv; postdiv 248 drivers/video/fbdev/gxt4500.c postdiv = pdiv1 * pdiv2; postdiv 249 drivers/video/fbdev/gxt4500.c pll_period = DIV_ROUND_UP(period_ps, postdiv); postdiv 257 drivers/video/fbdev/gxt4500.c n = intf * postdiv / period_ps; postdiv 260 drivers/video/fbdev/gxt4500.c t = par->refclk_ps * m * postdiv / n;