post_divr_freq     79 drivers/clk/analogbits/wrpll-cln28hpc.c static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
post_divr_freq     81 drivers/clk/analogbits/wrpll-cln28hpc.c 	if (post_divr_freq < MIN_POST_DIVR_FREQ ||
post_divr_freq     82 drivers/clk/analogbits/wrpll-cln28hpc.c 	    post_divr_freq > MAX_POST_DIVR_FREQ) {
post_divr_freq     84 drivers/clk/analogbits/wrpll-cln28hpc.c 		     __func__, post_divr_freq);
post_divr_freq     88 drivers/clk/analogbits/wrpll-cln28hpc.c 	switch (post_divr_freq) {
post_divr_freq    226 drivers/clk/analogbits/wrpll-cln28hpc.c 	u32 best_f, f, post_divr_freq;
post_divr_freq    277 drivers/clk/analogbits/wrpll-cln28hpc.c 		post_divr_freq = div_u64(parent_rate, r);
post_divr_freq    278 drivers/clk/analogbits/wrpll-cln28hpc.c 		vco_pre = fbdiv * post_divr_freq;
post_divr_freq    301 drivers/clk/analogbits/wrpll-cln28hpc.c 	post_divr_freq = div_u64(parent_rate, best_r);
post_divr_freq    304 drivers/clk/analogbits/wrpll-cln28hpc.c 	range = __wrpll_calc_filter_range(post_divr_freq);