post_divider 1061 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; post_divider 1078 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->post_divider = args.v6_out.ulClock.ucPostDiv; post_divider 49 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h u32 post_divider; post_divider 1321 drivers/gpu/drm/amd/amdgpu/cik.c tmp |= dividers.post_divider; post_divider 1370 drivers/gpu/drm/amd/amdgpu/cik.c tmp |= dividers.post_divider; post_divider 745 drivers/gpu/drm/amd/amdgpu/vi.c tmp |= dividers.post_divider; post_divider 835 drivers/gpu/drm/amd/amdgpu/vi.c tmp |= dividers.post_divider; post_divider 139 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t post_divider, post_divider 146 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; post_divider 198 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t post_divider, post_divider 211 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c post_divider, post_divider 222 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c ref_divider * post_divider * post_divider 240 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->pix_clk_post_divider = post_divider; post_divider 244 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c actual_calculated_clock_100hz * post_divider / 10; post_divider 260 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c uint32_t post_divider; post_divider 271 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c post_divider = max_post_divider; post_divider 272 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c post_divider >= min_post_divider; post_divider 273 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c --post_divider) { post_divider 282 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c post_divider, post_divider 2673 drivers/gpu/drm/radeon/ci_dpm.c table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; post_divider 2681 drivers/gpu/drm/radeon/ci_dpm.c table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; post_divider 2714 drivers/gpu/drm/radeon/ci_dpm.c table->VceLevel[count].Divider = (u8)dividers.post_divider; post_divider 2747 drivers/gpu/drm/radeon/ci_dpm.c table->AcpLevel[count].Divider = (u8)dividers.post_divider; post_divider 2779 drivers/gpu/drm/radeon/ci_dpm.c table->SamuLevel[count].Divider = (u8)dividers.post_divider; post_divider 3018 drivers/gpu/drm/radeon/ci_dpm.c table->ACPILevel.SclkDid = (u8)dividers.post_divider; post_divider 3210 drivers/gpu/drm/radeon/ci_dpm.c sclk->SclkDid = (u8)dividers.post_divider; post_divider 9442 drivers/gpu/drm/radeon/cik.c tmp |= dividers.post_divider; post_divider 9489 drivers/gpu/drm/radeon/cik.c tmp |= dividers.post_divider; post_divider 2929 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; post_divider 2946 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_divider = args.v6_out.ulClock.ucPostDiv; post_divider 742 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t post_divider = 0; post_divider 820 drivers/gpu/drm/radeon/radeon_legacy_crtc.c &reference_div, &post_divider); post_divider 823 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if (post_div->divider == post_divider) post_divider 834 drivers/gpu/drm/radeon/radeon_legacy_crtc.c post_divider); post_divider 601 drivers/gpu/drm/radeon/radeon_mode.h u32 post_divider; post_divider 150 drivers/gpu/drm/radeon/rv6xx_dpm.c step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); post_divider 152 drivers/gpu/drm/radeon/rv6xx_dpm.c step->post_divider = 1; post_divider 154 drivers/gpu/drm/radeon/rv6xx_dpm.c step->vco_frequency = clock * step->post_divider; post_divider 173 drivers/gpu/drm/radeon/rv6xx_dpm.c if (step->post_divider == 1) post_divider 176 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 lo_len = (step->post_divider - 2) / 2; post_divider 177 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 hi_len = step->post_divider - 2 - lo_len; post_divider 199 drivers/gpu/drm/radeon/rv6xx_dpm.c next.post_divider = cur->post_divider; post_divider 213 drivers/gpu/drm/radeon/rv6xx_dpm.c return (cur->post_divider > target->post_divider) && post_divider 214 drivers/gpu/drm/radeon/rv6xx_dpm.c ((cur->vco_frequency * target->post_divider) <= post_divider 215 drivers/gpu/drm/radeon/rv6xx_dpm.c (target->vco_frequency * (cur->post_divider - 1))); post_divider 225 drivers/gpu/drm/radeon/rv6xx_dpm.c next.post_divider--; post_divider 255 drivers/gpu/drm/radeon/rv6xx_dpm.c if (target.post_divider > cur.post_divider) post_divider 256 drivers/gpu/drm/radeon/rv6xx_dpm.c cur.post_divider = target.post_divider; post_divider 269 drivers/gpu/drm/radeon/rv6xx_dpm.c tiny.post_divider = next.post_divider; post_divider 274 drivers/gpu/drm/radeon/rv6xx_dpm.c if ((next.post_divider != target.post_divider) && post_divider 279 drivers/gpu/drm/radeon/rv6xx_dpm.c final_vco.post_divider = next.post_divider; post_divider 34 drivers/gpu/drm/radeon/rv6xx_dpm.h u32 post_divider; post_divider 52 drivers/gpu/drm/radeon/rv730_dpm.c u32 reference_divider, post_divider; post_divider 64 drivers/gpu/drm/radeon/rv730_dpm.c post_divider = ((dividers.post_div >> 4) & 0xf) + post_divider 67 drivers/gpu/drm/radeon/rv730_dpm.c post_divider = 1; post_divider 69 drivers/gpu/drm/radeon/rv730_dpm.c tmp = (u64) engine_clock * reference_divider * post_divider * 16384; post_divider 92 drivers/gpu/drm/radeon/rv730_dpm.c u32 vco_freq = engine_clock * post_divider; post_divider 131 drivers/gpu/drm/radeon/rv730_dpm.c u32 post_divider, reference_divider; post_divider 142 drivers/gpu/drm/radeon/rv730_dpm.c post_divider = ((dividers.post_div >> 4) & 0xf) + post_divider 145 drivers/gpu/drm/radeon/rv730_dpm.c post_divider = 1; post_divider 167 drivers/gpu/drm/radeon/rv730_dpm.c u32 vco_freq = memory_clock * post_divider; post_divider 324 drivers/gpu/drm/radeon/rv770_dpm.c u32 post_divider, reference_divider, feedback_divider8; post_divider 332 drivers/gpu/drm/radeon/rv770_dpm.c post_divider = dividers->post_div; post_divider 336 drivers/gpu/drm/radeon/rv770_dpm.c (8 * fyclk * reference_divider * post_divider) / reference_clock; post_divider 501 drivers/gpu/drm/radeon/rv770_dpm.c u32 reference_divider, post_divider; post_divider 513 drivers/gpu/drm/radeon/rv770_dpm.c post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; post_divider 515 drivers/gpu/drm/radeon/rv770_dpm.c post_divider = 1; post_divider 517 drivers/gpu/drm/radeon/rv770_dpm.c tmp = (u64) engine_clock * reference_divider * post_divider * 16384; post_divider 539 drivers/gpu/drm/radeon/rv770_dpm.c u32 vco_freq = engine_clock * post_divider; post_divider 431 drivers/video/fbdev/aty/aty128fb.c u32 post_divider; post_divider 1350 drivers/video/fbdev/aty/aty128fb.c div3 |= post_conv[pll->post_divider] << 16; post_divider 1388 drivers/video/fbdev/aty/aty128fb.c pll->post_divider = post_dividers[i]; post_divider 1404 drivers/video/fbdev/aty/aty128fb.c "vclk_per: %d\n", pll->post_divider, post_divider 79 drivers/video/fbdev/aty/atyfb.h u32 post_divider; post_divider 346 drivers/video/fbdev/aty/mach64_gx.c u32 post_divider; post_divider 352 drivers/video/fbdev/aty/mach64_gx.c post_divider = 1; post_divider 363 drivers/video/fbdev/aty/mach64_gx.c post_divider *= 2; post_divider 374 drivers/video/fbdev/aty/mach64_gx.c switch (post_divider) { post_divider 394 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.post_divider = post_divider; post_divider 560 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.post_divider = divider; /* fuer nix */ post_divider 679 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.post_divider = 0; post_divider 797 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.post_divider = divider; /* fuer nix */ post_divider 1709 drivers/video/fbdev/aty/radeon_base.c (rinfo->panel_info.post_divider << 16); post_divider 200 drivers/video/fbdev/aty/radeon_monitor.c rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48); post_divider 207 drivers/video/fbdev/aty/radeon_monitor.c pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider); post_divider 671 drivers/video/fbdev/aty/radeon_monitor.c rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7; post_divider 677 drivers/video/fbdev/aty/radeon_monitor.c (rinfo->panel_info.post_divider << 16), post_divider 265 drivers/video/fbdev/aty/radeonfb.h int post_divider;