post_div_min 126 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c unsigned post_div_min, post_div_max, post_div; post_div_min 154 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_min = pll->post_div; post_div_min 172 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_min = vco_min / target_clock; post_div_min 173 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if ((target_clock * post_div_min) < vco_min) post_div_min 174 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ++post_div_min; post_div_min 175 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (post_div_min < pll->min_post_div) post_div_min 176 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_min = pll->min_post_div; post_div_min 190 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c amdgpu_pll_reduce_ratio(&nom, &den, fb_div_min, post_div_min); post_div_min 194 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_best = post_div_min; post_div_min 199 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { post_div_min 967 drivers/gpu/drm/radeon/radeon_display.c unsigned post_div_min, post_div_max, post_div; post_div_min 998 drivers/gpu/drm/radeon/radeon_display.c post_div_min = pll->post_div; post_div_min 1016 drivers/gpu/drm/radeon/radeon_display.c post_div_min = vco_min / target_clock; post_div_min 1017 drivers/gpu/drm/radeon/radeon_display.c if ((target_clock * post_div_min) < vco_min) post_div_min 1018 drivers/gpu/drm/radeon/radeon_display.c ++post_div_min; post_div_min 1019 drivers/gpu/drm/radeon/radeon_display.c if (post_div_min < pll->min_post_div) post_div_min 1020 drivers/gpu/drm/radeon/radeon_display.c post_div_min = pll->min_post_div; post_div_min 1034 drivers/gpu/drm/radeon/radeon_display.c avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); post_div_min 1038 drivers/gpu/drm/radeon/radeon_display.c post_div_best = post_div_min; post_div_min 1043 drivers/gpu/drm/radeon/radeon_display.c for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {