post_div_m        362 drivers/clk/ti/fapll.c 	u32 post_div_m;
post_div_m        365 drivers/clk/ti/fapll.c 	post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
post_div_m        366 drivers/clk/ti/fapll.c 	frac_rate = current_rate * post_div_m;
post_div_m        375 drivers/clk/ti/fapll.c 	u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
post_div_m        377 drivers/clk/ti/fapll.c 	post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
post_div_m        378 drivers/clk/ti/fapll.c 	post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
post_div_m        379 drivers/clk/ti/fapll.c 	if (post_div_m > SYNTH_MAX_DIV_M)
post_div_m        381 drivers/clk/ti/fapll.c 	if (!post_div_m)
post_div_m        382 drivers/clk/ti/fapll.c 		post_div_m = 1;
post_div_m        384 drivers/clk/ti/fapll.c 	for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
post_div_m        388 drivers/clk/ti/fapll.c 						 rate * post_div_m);
post_div_m        406 drivers/clk/ti/fapll.c 	return post_div_m;
post_div_m        449 drivers/clk/ti/fapll.c 	u32 post_div_m = 0, v;
post_div_m        460 drivers/clk/ti/fapll.c 		post_div_m = DIV_ROUND_UP(frac_rate, rate);
post_div_m        461 drivers/clk/ti/fapll.c 		if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
post_div_m        462 drivers/clk/ti/fapll.c 			post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
post_div_m        469 drivers/clk/ti/fapll.c 		post_div_m = ti_fapll_synth_set_frac_rate(synth,
post_div_m        475 drivers/clk/ti/fapll.c 	v |= post_div_m;