post_div 1764 drivers/clk/clk-stm32f4.c const struct stm32f4_pll_post_div_data *post_div; post_div 1767 drivers/clk/clk-stm32f4.c post_div = &post_div_data[n]; post_div 1769 drivers/clk/clk-stm32f4.c hw = clk_register_pll_div(post_div->name, post_div 1770 drivers/clk/clk-stm32f4.c post_div->parent, post_div 1771 drivers/clk/clk-stm32f4.c post_div->flag, post_div 1772 drivers/clk/clk-stm32f4.c base + post_div->offset, post_div 1773 drivers/clk/clk-stm32f4.c post_div->shift, post_div 1774 drivers/clk/clk-stm32f4.c post_div->width, post_div 1775 drivers/clk/clk-stm32f4.c post_div->flag_div, post_div 1776 drivers/clk/clk-stm32f4.c post_div->div_table, post_div 1777 drivers/clk/clk-stm32f4.c clks[post_div->pll_num], post_div 1780 drivers/clk/clk-stm32f4.c if (post_div->idx != NO_IDX) post_div 1781 drivers/clk/clk-stm32f4.c clks[post_div->idx] = hw; post_div 1023 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->post_div = args.v3.ucPostDiv; post_div 1043 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->post_div = args.v5.ucPostDiv; post_div 1061 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; post_div 1075 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->post_div = args.v6_out.ucPllPostDiv; post_div 1115 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c mpll_param->post_div = args.ucPostDiv; post_div 28 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h u32 post_div; post_div 68 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h u32 post_div; post_div 196 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t post_div; post_div 83 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, post_div 88 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div_max = min(128 / post_div, ref_div_max); post_div 91 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); post_div 92 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); post_div 126 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c unsigned post_div_min, post_div_max, post_div; post_div 154 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_min = pll->post_div; post_div 155 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_max = pll->post_div; post_div 199 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { post_div 201 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, post_div 204 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c (ref_div * post_div)); post_div 209 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_best = post_div; post_div 213 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div = post_div_best; post_div 216 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, post_div 244 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c (ref_div * post_div * 10); post_div 246 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *post_div_p = post_div; post_div 250 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div, post_div); post_div 585 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c u32 post_div, post_div 612 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v1.ucPostDiv = post_div; post_div 622 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v2.ucPostDiv = post_div; post_div 632 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.ucPostDiv = post_div; post_div 649 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucPostDiv = post_div; post_div 679 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v6.ucPostDiv = post_div; post_div 826 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; post_div 852 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c pll->post_div = amdgpu_crtc->pll_post_div; post_div 855 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); post_div 862 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c ref_div, fb_div, frac_fb_div, post_div, post_div 51 drivers/gpu/drm/amd/amdgpu/atombios_crtc.h u32 post_div, post_div 673 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->graphics_level[index].SclkDid = (u8)dividers.post_div; post_div 932 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; post_div 938 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; post_div 1000 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->vce_level[i].Divider = (u8)dividers.post_div; post_div 1063 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->samu_level[i].Divider = (u8)dividers.post_div; post_div 1122 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->acp_level[i].Divider = (u8)dividers.post_div; post_div 5270 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; post_div 5276 drivers/gpu/drm/amd/amdgpu/si_dpm.c spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); post_div 5287 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 vco_freq = engine_clock * dividers.post_div; post_div 5368 drivers/gpu/drm/amd/amdgpu/si_dpm.c mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); post_div 5373 drivers/gpu/drm/amd/amdgpu/si_dpm.c YCLK_POST_DIV(mpll_param.post_div); post_div 55 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c u32 post_div = 0; post_div 61 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); post_div 64 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; post_div 74 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c clock = clock / post_div; post_div 832 drivers/gpu/drm/radeon/atombios_crtc.c u32 post_div, post_div 859 drivers/gpu/drm/radeon/atombios_crtc.c args.v1.ucPostDiv = post_div; post_div 869 drivers/gpu/drm/radeon/atombios_crtc.c args.v2.ucPostDiv = post_div; post_div 879 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.ucPostDiv = post_div; post_div 896 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucPostDiv = post_div; post_div 925 drivers/gpu/drm/radeon/atombios_crtc.c args.v6.ucPostDiv = post_div; post_div 1072 drivers/gpu/drm/radeon/atombios_crtc.c u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; post_div 1099 drivers/gpu/drm/radeon/atombios_crtc.c pll->post_div = radeon_crtc->pll_post_div; post_div 1104 drivers/gpu/drm/radeon/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); post_div 1107 drivers/gpu/drm/radeon/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); post_div 1110 drivers/gpu/drm/radeon/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); post_div 1117 drivers/gpu/drm/radeon/atombios_crtc.c ref_div, fb_div, frac_fb_div, post_div, post_div 2819 drivers/gpu/drm/radeon/ci_dpm.c mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); post_div 2824 drivers/gpu/drm/radeon/ci_dpm.c YCLK_POST_DIV(mpll_param.post_div); post_div 2834 drivers/gpu/drm/radeon/ci_dpm.c freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); post_div 2836 drivers/gpu/drm/radeon/ci_dpm.c freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); post_div 3189 drivers/gpu/drm/radeon/ci_dpm.c u32 vco_freq = engine_clock * dividers.post_div; post_div 510 drivers/gpu/drm/radeon/cypress_dpm.c dividers.post_div = 1; post_div 521 drivers/gpu/drm/radeon/cypress_dpm.c mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); post_div 538 drivers/gpu/drm/radeon/cypress_dpm.c mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); post_div 556 drivers/gpu/drm/radeon/cypress_dpm.c u32 vco_freq = memory_clock * dividers.post_div; post_div 1156 drivers/gpu/drm/radeon/evergreen.c WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK)); post_div 547 drivers/gpu/drm/radeon/kv_dpm.c pi->graphics_level[index].SclkDid = (u8)dividers.post_div; post_div 850 drivers/gpu/drm/radeon/kv_dpm.c pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; post_div 856 drivers/gpu/drm/radeon/kv_dpm.c pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; post_div 918 drivers/gpu/drm/radeon/kv_dpm.c pi->vce_level[i].Divider = (u8)dividers.post_div; post_div 981 drivers/gpu/drm/radeon/kv_dpm.c pi->samu_level[i].Divider = (u8)dividers.post_div; post_div 1040 drivers/gpu/drm/radeon/kv_dpm.c pi->acp_level[i].Divider = (u8)dividers.post_div; post_div 2740 drivers/gpu/drm/radeon/ni.c WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK)); post_div 2025 drivers/gpu/drm/radeon/ni_dpm.c tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; post_div 2031 drivers/gpu/drm/radeon/ni_dpm.c spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); post_div 2042 drivers/gpu/drm/radeon/ni_dpm.c u32 vco_freq = engine_clock * dividers.post_div; post_div 2192 drivers/gpu/drm/radeon/ni_dpm.c dividers.post_div = 1; post_div 2203 drivers/gpu/drm/radeon/ni_dpm.c mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); post_div 2220 drivers/gpu/drm/radeon/ni_dpm.c mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); post_div 2238 drivers/gpu/drm/radeon/ni_dpm.c u32 vco_freq = memory_clock * dividers.post_div; post_div 2861 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_div = args.v1.ucPostDiv; post_div 2875 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_div = args.v2.ucPostDiv; post_div 2890 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_div = args.v3.ucPostDiv; post_div 2910 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_div = args.v5.ucPostDiv; post_div 2929 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; post_div 2943 drivers/gpu/drm/radeon/radeon_atombios.c dividers->post_div = args.v6_out.ucPllPostDiv; post_div 2983 drivers/gpu/drm/radeon/radeon_atombios.c mpll_param->post_div = args.ucPostDiv; post_div 42 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t fb_div, ref_div, post_div, sclk; post_div 57 drivers/gpu/drm/radeon/radeon_clocks.c post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; post_div 58 drivers/gpu/drm/radeon/radeon_clocks.c if (post_div == 2) post_div 60 drivers/gpu/drm/radeon/radeon_clocks.c else if (post_div == 3) post_div 62 drivers/gpu/drm/radeon/radeon_clocks.c else if (post_div == 4) post_div 72 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t fb_div, ref_div, post_div, mclk; post_div 87 drivers/gpu/drm/radeon/radeon_clocks.c post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; post_div 88 drivers/gpu/drm/radeon/radeon_clocks.c if (post_div == 2) post_div 90 drivers/gpu/drm/radeon/radeon_clocks.c else if (post_div == 3) post_div 92 drivers/gpu/drm/radeon/radeon_clocks.c else if (post_div == 4) post_div 352 drivers/gpu/drm/radeon/radeon_clocks.c int *fb_div, int *post_div) post_div 363 drivers/gpu/drm/radeon/radeon_clocks.c *post_div = 8; post_div 366 drivers/gpu/drm/radeon/radeon_clocks.c *post_div = 4; post_div 369 drivers/gpu/drm/radeon/radeon_clocks.c *post_div = 2; post_div 372 drivers/gpu/drm/radeon/radeon_clocks.c *post_div = 1; post_div 383 drivers/gpu/drm/radeon/radeon_clocks.c req_clock /= *post_div; post_div 393 drivers/gpu/drm/radeon/radeon_clocks.c int fb_div, post_div; post_div 397 drivers/gpu/drm/radeon/radeon_clocks.c eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div); post_div 429 drivers/gpu/drm/radeon/radeon_clocks.c if ((eng_clock * post_div) >= 90000) post_div 449 drivers/gpu/drm/radeon/radeon_clocks.c switch (post_div) { post_div 924 drivers/gpu/drm/radeon/radeon_display.c static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, post_div 929 drivers/gpu/drm/radeon/radeon_display.c ref_div_max = max(min(100 / post_div, ref_div_max), 1u); post_div 932 drivers/gpu/drm/radeon/radeon_display.c *ref_div = min(max(den/post_div, 1u), ref_div_max); post_div 933 drivers/gpu/drm/radeon/radeon_display.c *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); post_div 967 drivers/gpu/drm/radeon/radeon_display.c unsigned post_div_min, post_div_max, post_div; post_div 998 drivers/gpu/drm/radeon/radeon_display.c post_div_min = pll->post_div; post_div 999 drivers/gpu/drm/radeon/radeon_display.c post_div_max = pll->post_div; post_div 1043 drivers/gpu/drm/radeon/radeon_display.c for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { post_div 1045 drivers/gpu/drm/radeon/radeon_display.c avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, post_div 1048 drivers/gpu/drm/radeon/radeon_display.c (ref_div * post_div)); post_div 1053 drivers/gpu/drm/radeon/radeon_display.c post_div_best = post_div; post_div 1057 drivers/gpu/drm/radeon/radeon_display.c post_div = post_div_best; post_div 1060 drivers/gpu/drm/radeon/radeon_display.c avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, post_div 1088 drivers/gpu/drm/radeon/radeon_display.c (ref_div * post_div * 10); post_div 1090 drivers/gpu/drm/radeon/radeon_display.c *post_div_p = post_div; post_div 1094 drivers/gpu/drm/radeon/radeon_display.c ref_div, post_div); post_div 1130 drivers/gpu/drm/radeon/radeon_display.c uint32_t post_div; post_div 1163 drivers/gpu/drm/radeon/radeon_display.c min_post_div = max_post_div = pll->post_div; post_div 1170 drivers/gpu/drm/radeon/radeon_display.c for (post_div = max_post_div; post_div >= min_post_div; --post_div) { post_div 1173 drivers/gpu/drm/radeon/radeon_display.c if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) post_div 1178 drivers/gpu/drm/radeon/radeon_display.c if ((post_div == 5) || post_div 1179 drivers/gpu/drm/radeon/radeon_display.c (post_div == 7) || post_div 1180 drivers/gpu/drm/radeon/radeon_display.c (post_div == 9) || post_div 1181 drivers/gpu/drm/radeon/radeon_display.c (post_div == 10) || post_div 1182 drivers/gpu/drm/radeon/radeon_display.c (post_div == 11) || post_div 1183 drivers/gpu/drm/radeon/radeon_display.c (post_div == 13) || post_div 1184 drivers/gpu/drm/radeon/radeon_display.c (post_div == 14) || post_div 1185 drivers/gpu/drm/radeon/radeon_display.c (post_div == 15)) post_div 1222 drivers/gpu/drm/radeon/radeon_display.c current_freq = radeon_div(tmp, ref_div * post_div); post_div 1237 drivers/gpu/drm/radeon/radeon_display.c best_post_div = post_div; post_div 1246 drivers/gpu/drm/radeon/radeon_display.c best_post_div = post_div; post_div 1257 drivers/gpu/drm/radeon/radeon_display.c ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || post_div 1258 drivers/gpu/drm/radeon/radeon_display.c ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { post_div 1259 drivers/gpu/drm/radeon/radeon_display.c best_post_div = post_div; post_div 756 drivers/gpu/drm/radeon/radeon_legacy_crtc.c } *post_div, post_divs[] = { post_div 822 drivers/gpu/drm/radeon/radeon_legacy_crtc.c for (post_div = &post_divs[0]; post_div->divider; ++post_div) { post_div 823 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if (post_div->divider == post_divider) post_div 827 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if (!post_div->divider) post_div 828 drivers/gpu/drm/radeon/radeon_legacy_crtc.c post_div = &post_divs[0]; post_div 843 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); post_div 862 drivers/gpu/drm/radeon/radeon_legacy_tv.c int post_div; post_div 864 drivers/gpu/drm/radeon/radeon_legacy_tv.c case 1: post_div = 0; break; post_div 865 drivers/gpu/drm/radeon/radeon_legacy_tv.c case 2: post_div = 1; break; post_div 866 drivers/gpu/drm/radeon/radeon_legacy_tv.c case 3: post_div = 4; break; post_div 867 drivers/gpu/drm/radeon/radeon_legacy_tv.c case 4: post_div = 2; break; post_div 868 drivers/gpu/drm/radeon/radeon_legacy_tv.c case 6: post_div = 6; break; post_div 869 drivers/gpu/drm/radeon/radeon_legacy_tv.c case 8: post_div = 3; break; post_div 870 drivers/gpu/drm/radeon/radeon_legacy_tv.c case 12: post_div = 7; break; post_div 872 drivers/gpu/drm/radeon/radeon_legacy_tv.c default: post_div = 5; break; post_div 874 drivers/gpu/drm/radeon/radeon_legacy_tv.c return post_div; post_div 171 drivers/gpu/drm/radeon/radeon_mode.h uint32_t post_div; post_div 580 drivers/gpu/drm/radeon/radeon_mode.h u32 post_div; post_div 620 drivers/gpu/drm/radeon/radeon_mode.h u32 post_div; post_div 922 drivers/gpu/drm/radeon/radeon_uvd.c unsigned post_div = vco_freq / target_freq; post_div 925 drivers/gpu/drm/radeon/radeon_uvd.c if (post_div < pd_min) post_div 926 drivers/gpu/drm/radeon/radeon_uvd.c post_div = pd_min; post_div 929 drivers/gpu/drm/radeon/radeon_uvd.c if ((vco_freq / post_div) > target_freq) post_div 930 drivers/gpu/drm/radeon/radeon_uvd.c post_div += 1; post_div 933 drivers/gpu/drm/radeon/radeon_uvd.c if (post_div > pd_even && post_div % 2) post_div 934 drivers/gpu/drm/radeon/radeon_uvd.c post_div += 1; post_div 936 drivers/gpu/drm/radeon/radeon_uvd.c return post_div; post_div 90 drivers/gpu/drm/radeon/rs780_dpm.c r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); post_div 456 drivers/gpu/drm/radeon/rs780_dpm.c (min_dividers.post_div != max_dividers.post_div) || post_div 458 drivers/gpu/drm/radeon/rs780_dpm.c (max_dividers.post_div != current_max_dividers.post_div)) post_div 991 drivers/gpu/drm/radeon/rs780_dpm.c u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + post_div 994 drivers/gpu/drm/radeon/rs780_dpm.c (post_div * ref_div); post_div 1013 drivers/gpu/drm/radeon/rs780_dpm.c u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + post_div 1016 drivers/gpu/drm/radeon/rs780_dpm.c (post_div * ref_div); post_div 150 drivers/gpu/drm/radeon/rv6xx_dpm.c step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); post_div 608 drivers/gpu/drm/radeon/rv6xx_dpm.c rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div); post_div 64 drivers/gpu/drm/radeon/rv730_dpm.c post_divider = ((dividers.post_div >> 4) & 0xf) + post_div 65 drivers/gpu/drm/radeon/rv730_dpm.c (dividers.post_div & 0xf) + 2; post_div 80 drivers/gpu/drm/radeon/rv730_dpm.c spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); post_div 81 drivers/gpu/drm/radeon/rv730_dpm.c spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); post_div 142 drivers/gpu/drm/radeon/rv730_dpm.c post_divider = ((dividers.post_div >> 4) & 0xf) + post_div 143 drivers/gpu/drm/radeon/rv730_dpm.c (dividers.post_div & 0xf) + 2; post_div 155 drivers/gpu/drm/radeon/rv730_dpm.c mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); post_div 156 drivers/gpu/drm/radeon/rv730_dpm.c mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); post_div 143 drivers/gpu/drm/radeon/rv740_dpm.c tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; post_div 149 drivers/gpu/drm/radeon/rv740_dpm.c spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); post_div 160 drivers/gpu/drm/radeon/rv740_dpm.c u32 vco_freq = engine_clock * dividers.post_div; post_div 217 drivers/gpu/drm/radeon/rv740_dpm.c mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); post_div 234 drivers/gpu/drm/radeon/rv740_dpm.c mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); post_div 247 drivers/gpu/drm/radeon/rv740_dpm.c u32 vco_freq = memory_clock * dividers.post_div; post_div 332 drivers/gpu/drm/radeon/rv770_dpm.c post_divider = dividers->post_div; post_div 421 drivers/gpu/drm/radeon/rv770_dpm.c ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); post_div 451 drivers/gpu/drm/radeon/rv770_dpm.c ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); post_div 513 drivers/gpu/drm/radeon/rv770_dpm.c post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; post_div 527 drivers/gpu/drm/radeon/rv770_dpm.c spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); post_div 528 drivers/gpu/drm/radeon/rv770_dpm.c spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); post_div 4808 drivers/gpu/drm/radeon/si_dpm.c tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; post_div 4814 drivers/gpu/drm/radeon/si_dpm.c spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); post_div 4825 drivers/gpu/drm/radeon/si_dpm.c u32 vco_freq = engine_clock * dividers.post_div; post_div 4906 drivers/gpu/drm/radeon/si_dpm.c mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); post_div 4911 drivers/gpu/drm/radeon/si_dpm.c YCLK_POST_DIV(mpll_param.post_div); post_div 559 drivers/gpu/drm/radeon/sumo_dpm.c sumo_set_divider_value(rdev, index, dividers.post_div); post_div 795 drivers/gpu/drm/radeon/sumo_dpm.c WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK); post_div 383 drivers/gpu/drm/radeon/trinity_dpm.c value |= PDS_DIV(dividers.post_div); post_div 599 drivers/gpu/drm/radeon/trinity_dpm.c value |= CLK_DIVIDER(dividers.post_div); post_div 609 drivers/gpu/drm/radeon/trinity_dpm.c value |= PD_SCLK_DIVIDER(dividers.post_div); post_div 1053 drivers/media/tuners/tda18271-maps.c u32 *freq, u8 *post_div, u8 *div) post_div 1093 drivers/media/tuners/tda18271-maps.c *post_div = map[i].pd; post_div 1097 drivers/media/tuners/tda18271-maps.c i, map_name, *post_div, *div); post_div 180 drivers/media/tuners/tda18271-priv.h u32 *freq, u8 *post_div, u8 *div); post_div 1536 drivers/video/fbdev/aty/radeon_base.c } *post_div, post_div 1605 drivers/video/fbdev/aty/radeon_base.c for (post_div = &post_divs[0]; post_div->divider; ++post_div) { post_div 1606 drivers/video/fbdev/aty/radeon_base.c pll_output_freq = post_div->divider * freq; post_div 1610 drivers/video/fbdev/aty/radeon_base.c if (uses_dvo && (post_div->divider & 1)) post_div 1619 drivers/video/fbdev/aty/radeon_base.c if ( !post_div->divider ) { post_div 1620 drivers/video/fbdev/aty/radeon_base.c post_div = &post_divs[post_div->bitvalue]; post_div 1621 drivers/video/fbdev/aty/radeon_base.c pll_output_freq = post_div->divider * freq; post_div 1629 drivers/video/fbdev/aty/radeon_base.c if ( !post_div->divider ) { post_div 1630 drivers/video/fbdev/aty/radeon_base.c post_div = &post_divs[post_div->bitvalue]; post_div 1631 drivers/video/fbdev/aty/radeon_base.c pll_output_freq = post_div->divider * freq; post_div 1640 drivers/video/fbdev/aty/radeon_base.c regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); post_div 1642 drivers/video/fbdev/aty/radeon_base.c pr_debug("post div = 0x%x\n", post_div->bitvalue); post_div 233 drivers/video/fbdev/aty/radeonfb.h int post_div;