port_dpll_id     10092 drivers/gpu/drm/i915/display/intel_display.c 	enum icl_port_dpll_id port_dpll_id;
port_dpll_id     10100 drivers/gpu/drm/i915/display/intel_display.c 		port_dpll_id = ICL_PORT_DPLL_DEFAULT;
port_dpll_id     10107 drivers/gpu/drm/i915/display/intel_display.c 			port_dpll_id = ICL_PORT_DPLL_MG_PHY;
port_dpll_id     10111 drivers/gpu/drm/i915/display/intel_display.c 			port_dpll_id = ICL_PORT_DPLL_DEFAULT;
port_dpll_id     10118 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->icl_port_dplls[port_dpll_id].pll =
port_dpll_id     10121 drivers/gpu/drm/i915/display/intel_display.c 	icl_set_active_port_dpll(pipe_config, port_dpll_id);
port_dpll_id     2871 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 			      enum icl_port_dpll_id port_dpll_id)
port_dpll_id     2874 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		&crtc_state->icl_port_dplls[port_dpll_id];
port_dpll_id     2887 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
port_dpll_id     2896 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		port_dpll_id = ICL_PORT_DPLL_MG_PHY;
port_dpll_id     2898 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	icl_set_active_port_dpll(crtc_state, port_dpll_id);
port_dpll_id      366 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 			      enum icl_port_dpll_id port_dpll_id);