port_cap 478 drivers/gpu/drm/drm_dp_helper.c const u8 port_cap[4]) port_cap 480 drivers/gpu/drm/drm_dp_helper.c int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; port_cap 489 drivers/gpu/drm/drm_dp_helper.c return port_cap[1] * 8 * 1000; port_cap 493 drivers/gpu/drm/drm_dp_helper.c return port_cap[1] * 2500; port_cap 509 drivers/gpu/drm/drm_dp_helper.c const u8 port_cap[4]) port_cap 511 drivers/gpu/drm/drm_dp_helper.c int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; port_cap 524 drivers/gpu/drm/drm_dp_helper.c bpc = port_cap[2] & DP_DS_MAX_BPC_MASK; port_cap 566 drivers/gpu/drm/drm_dp_helper.c const u8 port_cap[4], struct drm_dp_aux *aux) port_cap 575 drivers/gpu/drm/drm_dp_helper.c int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; port_cap 625 drivers/gpu/drm/drm_dp_helper.c clk = drm_dp_downstream_max_clock(dpcd, port_cap); port_cap 634 drivers/gpu/drm/drm_dp_helper.c bpc = drm_dp_downstream_max_bpc(dpcd, port_cap); port_cap 80 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c struct hinic_port_cap port_cap; port_cap 91 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c err = hinic_port_get_cap(nic_dev, &port_cap); port_cap 102 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c set_link_speed(link_ksettings, port_cap.speed); port_cap 104 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c if (!!(port_cap.autoneg_cap & HINIC_AUTONEG_SUPPORTED)) port_cap 108 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c if (port_cap.autoneg_state == HINIC_AUTONEG_ACTIVE) port_cap 111 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.duplex = (port_cap.duplex == HINIC_DUPLEX_FULL) ? port_cap 349 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_port_cap *port_cap) port_cap 357 drivers/net/ethernet/huawei/hinic/hinic_port.c port_cap->func_idx = HINIC_HWIF_FUNC_IDX(hwif); port_cap 360 drivers/net/ethernet/huawei/hinic/hinic_port.c port_cap, sizeof(*port_cap), port_cap 361 drivers/net/ethernet/huawei/hinic/hinic_port.c port_cap, &out_size); port_cap 362 drivers/net/ethernet/huawei/hinic/hinic_port.c if (err || (out_size != sizeof(*port_cap)) || port_cap->status) { port_cap 365 drivers/net/ethernet/huawei/hinic/hinic_port.c port_cap->status); port_cap 535 drivers/net/ethernet/huawei/hinic/hinic_port.h struct hinic_port_cap *port_cap); port_cap 157 drivers/net/ethernet/mellanox/mlx4/eq.c struct mlx4_port_cap port_cap; port_cap 159 drivers/net/ethernet/mellanox/mlx4/eq.c if (!mlx4_QUERY_PORT(dev, 1, &port_cap) && port_cap.link_state) port_cap 162 drivers/net/ethernet/mellanox/mlx4/eq.c if (!mlx4_QUERY_PORT(dev, 2, &port_cap) && port_cap.link_state) port_cap 1106 drivers/net/ethernet/mellanox/mlx4/fw.c err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); port_cap 1157 drivers/net/ethernet/mellanox/mlx4/fw.c dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, port_cap 1158 drivers/net/ethernet/mellanox/mlx4/fw.c dev_cap->port_cap[1].max_port_width); port_cap 1183 drivers/net/ethernet/mellanox/mlx4/fw.c int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) port_cap 1205 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->max_vl = field >> 4; port_cap 1207 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->ib_mtu = field >> 4; port_cap 1208 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->max_port_width = field & 0xf; port_cap 1210 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->max_gids = 1 << (field & 0xf); port_cap 1212 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->max_pkeys = 1 << (field & 0xf); port_cap 1232 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->link_state = (field & 0x80) >> 7; port_cap 1233 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->supported_port_types = field & 3; port_cap 1234 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->suggested_type = (field >> 3) & 1; port_cap 1235 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->default_sense = (field >> 4) & 1; port_cap 1236 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->dmfs_optimized_state = (field >> 5) & 1; port_cap 1238 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->ib_mtu = field & 0xf; port_cap 1240 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->max_port_width = field & 0xf; port_cap 1242 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->max_gids = 1 << (field >> 4); port_cap 1243 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->max_pkeys = 1 << (field & 0xf); port_cap 1245 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->max_vl = field & 0xf; port_cap 1246 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->max_tc_eth = field >> 4; port_cap 1248 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->log_max_macs = field & 0xf; port_cap 1249 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->log_max_vlans = field >> 4; port_cap 1250 drivers/net/ethernet/mellanox/mlx4/fw.c MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); port_cap 1251 drivers/net/ethernet/mellanox/mlx4/fw.c MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); port_cap 1253 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->trans_type = field32 >> 24; port_cap 1254 drivers/net/ethernet/mellanox/mlx4/fw.c port_cap->vendor_oui = field32 & 0xffffff; port_cap 1255 drivers/net/ethernet/mellanox/mlx4/fw.c MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); port_cap 1256 drivers/net/ethernet/mellanox/mlx4/fw.c MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); port_cap 1458 drivers/net/ethernet/mellanox/mlx4/fw.c struct mlx4_port_cap port_cap; port_cap 1460 drivers/net/ethernet/mellanox/mlx4/fw.c err = mlx4_QUERY_PORT(dev, other_port, &port_cap); port_cap 1463 drivers/net/ethernet/mellanox/mlx4/fw.c port_type |= (port_cap.link_state << 7); port_cap 132 drivers/net/ethernet/mellanox/mlx4/fw.h struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1]; port_cap 231 drivers/net/ethernet/mellanox/mlx4/fw.h int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap); port_cap 398 drivers/net/ethernet/mellanox/mlx4/main.c struct mlx4_port_cap *port_cap) port_cap 400 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.vl_cap[port] = port_cap->max_vl; port_cap 401 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; port_cap 402 drivers/net/ethernet/mellanox/mlx4/main.c dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; port_cap 403 drivers/net/ethernet/mellanox/mlx4/main.c dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; port_cap 407 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.gid_table_len[port] = port_cap->max_gids; port_cap 408 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.pkey_table_len[port] = port_cap->max_pkeys; port_cap 409 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.port_width_cap[port] = port_cap->max_port_width; port_cap 410 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; port_cap 411 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.max_tc_eth = port_cap->max_tc_eth; port_cap 412 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.def_mac[port] = port_cap->def_mac; port_cap 413 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.supported_type[port] = port_cap->supported_port_types; port_cap 414 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.suggested_type[port] = port_cap->suggested_type; port_cap 415 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.default_sense[port] = port_cap->default_sense; port_cap 416 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.trans_type[port] = port_cap->trans_type; port_cap 417 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.vendor_oui[port] = port_cap->vendor_oui; port_cap 418 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.wavelength[port] = port_cap->wavelength; port_cap 419 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.trans_code[port] = port_cap->trans_code; port_cap 425 drivers/net/ethernet/mellanox/mlx4/main.c struct mlx4_port_cap *port_cap) port_cap 429 drivers/net/ethernet/mellanox/mlx4/main.c err = mlx4_QUERY_PORT(dev, port, port_cap); port_cap 494 drivers/net/ethernet/mellanox/mlx4/main.c err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); port_cap 635 drivers/net/ethernet/mellanox/mlx4/main.c if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { port_cap 636 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; port_cap 640 drivers/net/ethernet/mellanox/mlx4/main.c if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { port_cap 641 drivers/net/ethernet/mellanox/mlx4/main.c dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; port_cap 2234 drivers/net/ethernet/mellanox/mlx4/main.c struct mlx4_port_cap port_cap; port_cap 2240 drivers/net/ethernet/mellanox/mlx4/main.c if (mlx4_dev_port(dev, i, &port_cap)) { port_cap 2245 drivers/net/ethernet/mellanox/mlx4/main.c (port_cap.dmfs_optimized_state == port_cap 2252 drivers/net/ethernet/mellanox/mlx4/main.c (port_cap.dmfs_optimized_state ? port_cap 58 drivers/usb/host/xhci-hub.c struct xhci_port_cap *port_cap = NULL; port_cap 72 drivers/usb/host/xhci-hub.c port_cap = &xhci->port_caps[i]; port_cap 79 drivers/usb/host/xhci-hub.c if (port_cap->psi_count) { port_cap 81 drivers/usb/host/xhci-hub.c ssa_count = port_cap->psi_uid_count * 2; port_cap 111 drivers/usb/host/xhci-hub.c if (usb3_1 && port_cap->psi_count) { port_cap 123 drivers/usb/host/xhci-hub.c bm_attrib |= (port_cap->psi_uid_count - 1) << 5; port_cap 136 drivers/usb/host/xhci-hub.c for (i = 0; i < port_cap->psi_count; i++) { port_cap 137 drivers/usb/host/xhci-hub.c psi = port_cap->psi[i]; port_cap 2129 drivers/usb/host/xhci-mem.c struct xhci_port_cap *port_cap; port_cap 2164 drivers/usb/host/xhci-mem.c port_cap = &xhci->port_caps[xhci->num_port_caps++]; port_cap 2168 drivers/usb/host/xhci-mem.c port_cap->maj_rev = major_revision; port_cap 2169 drivers/usb/host/xhci-mem.c port_cap->min_rev = minor_revision; port_cap 2170 drivers/usb/host/xhci-mem.c port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp); port_cap 2172 drivers/usb/host/xhci-mem.c if (port_cap->psi_count) { port_cap 2173 drivers/usb/host/xhci-mem.c port_cap->psi = kcalloc_node(port_cap->psi_count, port_cap 2174 drivers/usb/host/xhci-mem.c sizeof(*port_cap->psi), port_cap 2176 drivers/usb/host/xhci-mem.c if (!port_cap->psi) port_cap 2177 drivers/usb/host/xhci-mem.c port_cap->psi_count = 0; port_cap 2179 drivers/usb/host/xhci-mem.c port_cap->psi_uid_count++; port_cap 2180 drivers/usb/host/xhci-mem.c for (i = 0; i < port_cap->psi_count; i++) { port_cap 2181 drivers/usb/host/xhci-mem.c port_cap->psi[i] = readl(addr + 4 + i); port_cap 2186 drivers/usb/host/xhci-mem.c if (i && (XHCI_EXT_PORT_PSIV(port_cap->psi[i]) != port_cap 2187 drivers/usb/host/xhci-mem.c XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1]))) port_cap 2188 drivers/usb/host/xhci-mem.c port_cap->psi_uid_count++; port_cap 2191 drivers/usb/host/xhci-mem.c XHCI_EXT_PORT_PSIV(port_cap->psi[i]), port_cap 2192 drivers/usb/host/xhci-mem.c XHCI_EXT_PORT_PSIE(port_cap->psi[i]), port_cap 2193 drivers/usb/host/xhci-mem.c XHCI_EXT_PORT_PLT(port_cap->psi[i]), port_cap 2194 drivers/usb/host/xhci-mem.c XHCI_EXT_PORT_PFD(port_cap->psi[i]), port_cap 2195 drivers/usb/host/xhci-mem.c XHCI_EXT_PORT_LP(port_cap->psi[i]), port_cap 2196 drivers/usb/host/xhci-mem.c XHCI_EXT_PORT_PSIM(port_cap->psi[i])); port_cap 2231 drivers/usb/host/xhci-mem.c hw_port->port_cap = port_cap; port_cap 1719 drivers/usb/host/xhci.h struct xhci_port_cap *port_cap; port_cap 1373 include/drm/drm_dp_helper.h const u8 port_cap[4]); port_cap 1375 include/drm/drm_dp_helper.h const u8 port_cap[4]); port_cap 1378 include/drm/drm_dp_helper.h const u8 port_cap[4], struct drm_dp_aux *aux);