pool_mask 6845 drivers/net/ethernet/intel/igb/igb_main.c u32 pool_mask, vlvf_mask, i; pool_mask 6848 drivers/net/ethernet/intel/igb/igb_main.c pool_mask = E1000_VLVF_POOLSEL_MASK; pool_mask 6852 drivers/net/ethernet/intel/igb/igb_main.c pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + pool_mask 6868 drivers/net/ethernet/intel/igb/igb_main.c if (vlvf & pool_mask) pool_mask 578 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 vlvfb_mask, pool_mask, i; pool_mask 581 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c pool_mask = ~BIT(VMDQ_P(0) % 32); pool_mask 605 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c (bits[VMDQ_P(0) / 32] & pool_mask)) pool_mask 384 drivers/net/ethernet/marvell/octeontx2/af/mbox.h struct npa_pool_s pool_mask; pool_mask 112 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c memcpy(mask, &req->pool_mask, pool_mask 173 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c ena = (req->pool.ena & req->pool_mask.ena) | pool_mask 175 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c ~req->pool_mask.ena); pool_mask 215 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c aq_req.pool_mask.ena = 1;