pol_val           100 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c 	u16 pol_val = 0;
pol_val           105 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c 	pol_val |= phy->lane_polarity[0] << 0;
pol_val           106 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c 	pol_val |= phy->lane_polarity[1] << 3;
pol_val           107 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c 	pol_val |= phy->lane_polarity[2] << 2;
pol_val           108 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c 	pol_val |= phy->lane_polarity[3] << 1;
pol_val           120 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c 	REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);
pol_val           534 drivers/iio/accel/mma9551_core.c 	u8 reg, pol_mask, pol_val;
pol_val           580 drivers/iio/accel/mma9551_core.c 	pol_val = polarity ? pol_mask : 0;
pol_val           583 drivers/iio/accel/mma9551_core.c 					 pol_mask, pol_val);
pol_val           109 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c 	u16 pol_val = 0;
pol_val           114 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c 	pol_val |= phy->lane_polarity[0] << 0;
pol_val           115 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c 	pol_val |= phy->lane_polarity[1] << 3;
pol_val           116 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c 	pol_val |= phy->lane_polarity[2] << 2;
pol_val           117 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c 	pol_val |= phy->lane_polarity[3] << 1;
pol_val           129 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c 	REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);