podn_vdd_dep_in_backend 4854 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
podn_vdd_dep_in_backend 4871 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
podn_vdd_dep_in_backend 4872 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
podn_vdd_dep_in_backend 4877 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
podn_vdd_dep_in_backend 4879 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
podn_vdd_dep_in_backend 4903 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
podn_vdd_dep_in_backend 4905 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
podn_vdd_dep_in_backend 4906 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol;