podn_dpm_table_in_backend 4853 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
podn_dpm_table_in_backend 4870 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
podn_dpm_table_in_backend 4872 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
podn_dpm_table_in_backend 4876 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
podn_dpm_table_in_backend 4879 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
podn_dpm_table_in_backend 4893 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
podn_dpm_table_in_backend 4902 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
podn_dpm_table_in_backend 4904 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;