pnr_mul            47 arch/mips/cavium-octeon/csrc-octeon.c 		sdiv = rst_boot.s.pnr_mul;	/* I/O clock */
pnr_mul            54 arch/mips/cavium-octeon/csrc-octeon.c 		sdiv = rst_boot.s.pnr_mul;	/* I/O clock */
pnr_mul           722 arch/mips/cavium-octeon/setup.c 		octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
pnr_mul           727 arch/mips/cavium-octeon/setup.c 		octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
pnr_mul          2944 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          2958 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          2985 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          2999 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          3016 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          3030 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          3046 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          3060 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          3080 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          3094 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          3109 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul          3123 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t pnr_mul:6;
pnr_mul            57 arch/mips/include/asm/octeon/cvmx-rst-defs.h 		uint64_t pnr_mul:6;
pnr_mul            71 arch/mips/include/asm/octeon/cvmx-rst-defs.h 		uint64_t pnr_mul:6;
pnr_mul          1365 drivers/crypto/cavium/nitrox/nitrox_csr.h 		u64 pnr_mul : 6;
pnr_mul          1375 drivers/crypto/cavium/nitrox/nitrox_csr.h 		u64 pnr_mul : 6;
pnr_mul           619 drivers/crypto/cavium/nitrox/nitrox_hal.c 	ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;