pmsu_mp_base 102 arch/arm/mach-mvebu/pmsu.c static void __iomem *pmsu_mp_base; pmsu_mp_base 115 arch/arm/mach-mvebu/pmsu.c writel(__pa_symbol(boot_addr), pmsu_mp_base + pmsu_mp_base 194 arch/arm/mach-mvebu/pmsu.c pmsu_mp_base = ioremap(res.start, resource_size(&res)); pmsu_mp_base 195 arch/arm/mach-mvebu/pmsu.c if (!pmsu_mp_base) { pmsu_mp_base 211 arch/arm/mach-mvebu/pmsu.c if (pmsu_mp_base == NULL) pmsu_mp_base 215 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); pmsu_mp_base 217 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); pmsu_mp_base 232 arch/arm/mach-mvebu/pmsu.c if (pmsu_mp_base == NULL) pmsu_mp_base 240 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); pmsu_mp_base 247 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); pmsu_mp_base 249 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); pmsu_mp_base 256 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); pmsu_mp_base 260 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); pmsu_mp_base 262 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); pmsu_mp_base 346 arch/arm/mach-mvebu/pmsu.c if (pmsu_mp_base == NULL) pmsu_mp_base 349 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); pmsu_mp_base 351 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); pmsu_mp_base 354 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); pmsu_mp_base 359 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); pmsu_mp_base 459 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY); pmsu_mp_base 463 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY); pmsu_mp_base 546 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); pmsu_mp_base 550 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); pmsu_mp_base 553 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu)); pmsu_mp_base 555 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu)); pmsu_mp_base 564 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); pmsu_mp_base 566 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); pmsu_mp_base 578 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); pmsu_mp_base 580 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); pmsu_mp_base 583 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); pmsu_mp_base 585 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); pmsu_mp_base 594 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); pmsu_mp_base 604 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); pmsu_mp_base 606 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));