pmr 80 arch/arm64/include/asm/daifflags.h u64 pmr; pmr 88 arch/arm64/include/asm/daifflags.h pmr = GIC_PRIO_IRQOFF; pmr 90 arch/arm64/include/asm/daifflags.h pmr = GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET; pmr 112 arch/arm64/include/asm/daifflags.h gic_write_pmr(pmr); pmr 31 arch/arm64/include/asm/irqflags.h u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1); pmr 33 arch/arm64/include/asm/irqflags.h WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF); pmr 50 arch/arm64/include/asm/irqflags.h u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1); pmr 52 arch/arm64/include/asm/irqflags.h WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF); pmr 79 arch/arm64/kernel/process.c unsigned long pmr; pmr 89 arch/arm64/kernel/process.c pmr = gic_read_pmr(); pmr 94 arch/arm64/kernel/process.c gic_write_pmr(pmr); pmr 94 arch/arm64/kvm/vgic-sys-reg-v3.c vmcr.pmr = (p->regval & ICC_PMR_EL1_MASK) >> ICC_PMR_EL1_SHIFT; pmr 97 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = (vmcr.pmr << ICC_PMR_EL1_SHIFT) & ICC_PMR_EL1_MASK; pmr 280 arch/mips/include/asm/nile4.h extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); pmr 104 drivers/ata/sata_sis.c u8 pmr; pmr 110 drivers/ata/sata_sis.c pci_read_config_byte(pdev, SIS_PMR, &pmr); pmr 111 drivers/ata/sata_sis.c if ((pmr & SIS_PMR_COMBINED) == 0) pmr 187 drivers/ata/sata_sis.c u8 pmr; pmr 213 drivers/ata/sata_sis.c pci_read_config_byte(pdev, SIS_PMR, &pmr); pmr 219 drivers/ata/sata_sis.c switch (pmr & 0x30) { pmr 228 drivers/ata/sata_sis.c if ((pmr & SIS_PMR_COMBINED) == 0) { pmr 1210 drivers/gpu/drm/etnaviv/etnaviv_gpu.c const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; pmr 1212 drivers/gpu/drm/etnaviv/etnaviv_gpu.c if (pmr->flags == flags) pmr 1213 drivers/gpu/drm/etnaviv/etnaviv_gpu.c etnaviv_perfmon_process(gpu, pmr, submit->exec_state); pmr 1245 drivers/gpu/drm/etnaviv/etnaviv_gpu.c const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; pmr 1247 drivers/gpu/drm/etnaviv/etnaviv_gpu.c *pmr->bo_vma = pmr->sequence; pmr 538 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c const struct etnaviv_perfmon_request *pmr, u32 exec_state) pmr 543 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c u32 *bo = pmr->bo_vma; pmr 546 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c dom = meta->domains + pmr->domain; pmr 547 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c sig = &dom->signal[pmr->signal]; pmr 550 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c *(bo + pmr->offset) = val; pmr 36 drivers/gpu/drm/etnaviv/etnaviv_perfmon.h const struct etnaviv_perfmon_request *pmr, u32 exec_state); pmr 81 drivers/mtd/maps/scx200_docflash.c unsigned pmr; pmr 103 drivers/mtd/maps/scx200_docflash.c pmr = inl(scx200_cb_base + SCx200_PMR); pmr 117 drivers/mtd/maps/scx200_docflash.c if (pmr & (1<<6)) pmr 157 drivers/mtd/maps/scx200_docflash.c pmr = inl(scx200_cb_base + SCx200_PMR); pmr 160 drivers/mtd/maps/scx200_docflash.c pmr &= ~(1<<6); pmr 162 drivers/mtd/maps/scx200_docflash.c pmr |= (1<<6); pmr 164 drivers/mtd/maps/scx200_docflash.c outl(pmr, scx200_cb_base + SCx200_PMR); pmr 1595 net/ipv6/mcast.c struct mld2_report *pmr; pmr 1632 net/ipv6/mcast.c skb_put(skb, sizeof(*pmr)); pmr 1633 net/ipv6/mcast.c pmr = (struct mld2_report *)skb_transport_header(skb); pmr 1634 net/ipv6/mcast.c pmr->mld2r_type = ICMPV6_MLD2_REPORT; pmr 1635 net/ipv6/mcast.c pmr->mld2r_resv1 = 0; pmr 1636 net/ipv6/mcast.c pmr->mld2r_cksum = 0; pmr 1637 net/ipv6/mcast.c pmr->mld2r_resv2 = 0; pmr 1638 net/ipv6/mcast.c pmr->mld2r_ngrec = 0; pmr 1645 net/ipv6/mcast.c struct mld2_report *pmr = pmr 1663 net/ipv6/mcast.c pmr->mld2r_cksum = csum_ipv6_magic(&pip6->saddr, &pip6->daddr, mldlen, pmr 1709 net/ipv6/mcast.c struct mld2_report *pmr; pmr 1722 net/ipv6/mcast.c pmr = (struct mld2_report *)skb_transport_header(skb); pmr 1723 net/ipv6/mcast.c pmr->mld2r_ngrec = htons(ntohs(pmr->mld2r_ngrec)+1); pmr 1735 net/ipv6/mcast.c struct mld2_report *pmr; pmr 1760 net/ipv6/mcast.c pmr = skb ? (struct mld2_report *)skb_transport_header(skb) : NULL; pmr 1764 net/ipv6/mcast.c if (pmr && pmr->mld2r_ngrec && pmr 646 virt/kvm/arm/hyp/vgic-v3-sr.c u8 lr_prio, pmr; pmr 658 virt/kvm/arm/hyp/vgic-v3-sr.c pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; pmr 660 virt/kvm/arm/hyp/vgic-v3-sr.c if (pmr <= lr_prio) pmr 290 virt/kvm/arm/vgic/vgic-mmio-v2.c val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >> pmr 337 virt/kvm/arm/vgic/vgic-mmio-v2.c vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) & pmr 241 virt/kvm/arm/vgic/vgic-v2.c vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) << pmr 271 virt/kvm/arm/vgic/vgic-v2.c vmcrp->pmr = ((vmcr & GICH_VMCR_PRIMASK_MASK) >> pmr 228 virt/kvm/arm/vgic/vgic-v3.c vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK; pmr 261 virt/kvm/arm/vgic/vgic-v3.c vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; pmr 970 virt/kvm/arm/vgic/vgic.c irq->priority < vmcr.pmr; pmr 146 virt/kvm/arm/vgic/vgic.h u32 pmr; /* Priority mask field in the GICC_PMR and