pmc_enable 122 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c u64 pmc_enable = 0; pmc_enable 124 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c if (!(pmc_enable = nvkm_top_reset(device, devidx))) { pmc_enable 128 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c pmc_enable = map->stat; pmc_enable 135 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c return pmc_enable; pmc_enable 141 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c u64 pmc_enable = nvkm_mc_reset_mask(device, true, devidx); pmc_enable 142 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c if (pmc_enable) { pmc_enable 143 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_mask(device, 0x000200, pmc_enable, 0x00000000); pmc_enable 144 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_mask(device, 0x000200, pmc_enable, pmc_enable); pmc_enable 152 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); pmc_enable 153 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c if (pmc_enable) pmc_enable 154 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_mask(device, 0x000200, pmc_enable, 0x00000000); pmc_enable 160 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); pmc_enable 161 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c if (pmc_enable) { pmc_enable 162 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c nvkm_mask(device, 0x000200, pmc_enable, pmc_enable); pmc_enable 170 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); pmc_enable 172 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c return (pmc_enable != 0) && pmc_enable 173 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c ((nvkm_rd32(device, 0x000200) & pmc_enable) == pmc_enable); pmc_enable 118 tools/testing/selftests/powerpc/pmu/ebb/ebb.c if (ebb_state.pmc_enable[PMC_INDEX(i)]) pmc_enable 28 tools/testing/selftests/powerpc/pmu/ebb/ebb.h bool pmc_enable[6]; pmc_enable 43 tools/testing/selftests/powerpc/pmu/ebb/ebb.h ebb_state.pmc_enable[PMC_INDEX(pmc)] = true;