pmbase             58 drivers/char/hw_random/amd-rng.c 	u32 pmbase;
pmbase            132 drivers/char/hw_random/amd-rng.c 	u32 pmbase;
pmbase            144 drivers/char/hw_random/amd-rng.c 	err = pci_read_config_dword(pdev, 0x58, &pmbase);
pmbase            148 drivers/char/hw_random/amd-rng.c 	pmbase &= 0x0000FF00;
pmbase            149 drivers/char/hw_random/amd-rng.c 	if (pmbase == 0)
pmbase            156 drivers/char/hw_random/amd-rng.c 	if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
pmbase            158 drivers/char/hw_random/amd-rng.c 			pmbase + 0xF0);
pmbase            163 drivers/char/hw_random/amd-rng.c 	priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
pmbase            171 drivers/char/hw_random/amd-rng.c 	priv->pmbase = pmbase;
pmbase            185 drivers/char/hw_random/amd-rng.c 	release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
pmbase            201 drivers/char/hw_random/amd-rng.c 	release_region(priv->pmbase + PMBASE_OFFSET, PMBASE_SIZE);
pmbase             47 drivers/cpufreq/speedstep-ich.c static u32 pmbase;
pmbase             71 drivers/cpufreq/speedstep-ich.c 	pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
pmbase             72 drivers/cpufreq/speedstep-ich.c 	if (!(pmbase & 0x01)) {
pmbase             77 drivers/cpufreq/speedstep-ich.c 	pmbase &= 0xFFFFFFFE;
pmbase             78 drivers/cpufreq/speedstep-ich.c 	if (!pmbase) {
pmbase             83 drivers/cpufreq/speedstep-ich.c 	pr_debug("pmbase is 0x%x\n", pmbase);
pmbase            107 drivers/cpufreq/speedstep-ich.c 	value = inb(pmbase + 0x50);
pmbase            109 drivers/cpufreq/speedstep-ich.c 	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
pmbase            115 drivers/cpufreq/speedstep-ich.c 	pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);
pmbase            118 drivers/cpufreq/speedstep-ich.c 	pm2_blk = inb(pmbase + 0x20);
pmbase            120 drivers/cpufreq/speedstep-ich.c 	outb(pm2_blk, (pmbase + 0x20));
pmbase            123 drivers/cpufreq/speedstep-ich.c 	outb(value, (pmbase + 0x50));
pmbase            127 drivers/cpufreq/speedstep-ich.c 	outb(pm2_blk, (pmbase + 0x20));
pmbase            130 drivers/cpufreq/speedstep-ich.c 	value = inb(pmbase + 0x50);
pmbase            135 drivers/cpufreq/speedstep-ich.c 	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
pmbase             72 drivers/gpio/gpio-amd8111.c 	u32			pmbase;
pmbase            201 drivers/gpio/gpio-amd8111.c 	err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);
pmbase            205 drivers/gpio/gpio-amd8111.c 	gp.pmbase &= 0x0000FF00;
pmbase            206 drivers/gpio/gpio-amd8111.c 	if (gp.pmbase == 0)
pmbase            208 drivers/gpio/gpio-amd8111.c 	if (!devm_request_region(&pdev->dev, gp.pmbase + PMBASE_OFFSET,
pmbase            211 drivers/gpio/gpio-amd8111.c 			gp.pmbase + PMBASE_OFFSET);
pmbase            215 drivers/gpio/gpio-amd8111.c 	gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
pmbase            278 drivers/pci/quirks.c 	u32 pmbase;
pmbase            281 drivers/pci/quirks.c 	pci_read_config_dword(dev, 0x40, &pmbase);
pmbase            282 drivers/pci/quirks.c 	pmbase = pmbase & 0xff80;
pmbase            283 drivers/pci/quirks.c 	pm1a = inw(pmbase);
pmbase            287 drivers/pci/quirks.c 		outw(0x10, pmbase);