pm_regs           127 arch/powerpc/oprofile/op_model_cell.c } pm_regs;
pm_regs           291 arch/powerpc/oprofile/op_model_cell.c 		pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;
pm_regs           299 arch/powerpc/oprofile/op_model_cell.c 		pm_regs.pm07_cntrl[ctr] = 0;
pm_regs           315 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm07_cntrl[ctr] = 0;
pm_regs           316 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);
pm_regs           317 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);
pm_regs           318 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);
pm_regs           343 arch/powerpc/oprofile/op_model_cell.c 		pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);
pm_regs           345 arch/powerpc/oprofile/op_model_cell.c 		pm_regs.pm07_cntrl[ctr] = 0;
pm_regs           351 arch/powerpc/oprofile/op_model_cell.c 			pm_regs.debug_bus_control |=
pm_regs           357 arch/powerpc/oprofile/op_model_cell.c 					pm_regs.group_control |=
pm_regs           377 arch/powerpc/oprofile/op_model_cell.c 	if (pm_regs.pm_cntrl.enable == 1)
pm_regs           380 arch/powerpc/oprofile/op_model_cell.c 	if (pm_regs.pm_cntrl.stop_at_max == 1)
pm_regs           383 arch/powerpc/oprofile/op_model_cell.c 	if (pm_regs.pm_cntrl.trace_mode != 0)
pm_regs           384 arch/powerpc/oprofile/op_model_cell.c 		val |= CBE_PM_TRACE_MODE_SET(pm_regs.pm_cntrl.trace_mode);
pm_regs           386 arch/powerpc/oprofile/op_model_cell.c 	if (pm_regs.pm_cntrl.trace_buf_ovflw == 1)
pm_regs           387 arch/powerpc/oprofile/op_model_cell.c 		val |= CBE_PM_TRACE_BUF_OVFLW(pm_regs.pm_cntrl.trace_buf_ovflw);
pm_regs           388 arch/powerpc/oprofile/op_model_cell.c 	if (pm_regs.pm_cntrl.freeze == 1)
pm_regs           391 arch/powerpc/oprofile/op_model_cell.c 	val |= CBE_PM_SPU_ADDR_TRACE_SET(pm_regs.pm_cntrl.spu_addr_trace);
pm_regs           397 arch/powerpc/oprofile/op_model_cell.c 	val |= CBE_PM_COUNT_MODE_SET(pm_regs.pm_cntrl.count_mode);
pm_regs           411 arch/powerpc/oprofile/op_model_cell.c 			pm_regs.pm_cntrl.count_mode = CBE_COUNT_ALL_MODES;
pm_regs           413 arch/powerpc/oprofile/op_model_cell.c 			pm_regs.pm_cntrl.count_mode =
pm_regs           417 arch/powerpc/oprofile/op_model_cell.c 			pm_regs.pm_cntrl.count_mode = CBE_COUNT_PROBLEM_MODE;
pm_regs           419 arch/powerpc/oprofile/op_model_cell.c 			pm_regs.pm_cntrl.count_mode =
pm_regs           469 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.group_control = 0;
pm_regs           470 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.debug_bus_control = 0;
pm_regs           535 arch/powerpc/oprofile/op_model_cell.c 					   pm_regs.pm07_cntrl);
pm_regs           660 arch/powerpc/oprofile/op_model_cell.c 		enable_ctr(cpu, 0, pm_regs.pm07_cntrl);
pm_regs           708 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm_cntrl.trace_buf_ovflw = 1;
pm_regs           714 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm_cntrl.trace_mode = 2;
pm_regs           716 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm_cntrl.spu_addr_trace = 0x1;  /* using debug bus
pm_regs           843 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.group_control = 0;
pm_regs           844 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.debug_bus_control = 0;
pm_regs           845 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm_cntrl.stop_at_max = 1;
pm_regs           846 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm_cntrl.trace_mode = 0;
pm_regs           847 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm_cntrl.freeze = 1;
pm_regs           848 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm_cntrl.trace_buf_ovflw = 0;
pm_regs           849 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm_cntrl.spu_addr_trace = 0;
pm_regs           917 arch/powerpc/oprofile/op_model_cell.c 	cbe_write_pm(cpu, group_control, pm_regs.group_control);
pm_regs           918 arch/powerpc/oprofile/op_model_cell.c 	cbe_write_pm(cpu, debug_bus_control, pm_regs.debug_bus_control);
pm_regs          1366 arch/powerpc/oprofile/op_model_cell.c 			enable_ctr(cpu, 0, pm_regs.pm07_cntrl);
pm_regs          1412 arch/powerpc/oprofile/op_model_cell.c 				enable_ctr(cpu, i, pm_regs.pm07_cntrl);
pm_regs           134 drivers/tty/serial/mvebu-uart.c 	struct mvebu_uart_pm_regs pm_regs;
pm_regs           757 drivers/tty/serial/mvebu-uart.c 	mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
pm_regs           758 drivers/tty/serial/mvebu-uart.c 	mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
pm_regs           759 drivers/tty/serial/mvebu-uart.c 	mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
pm_regs           760 drivers/tty/serial/mvebu-uart.c 	mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
pm_regs           761 drivers/tty/serial/mvebu-uart.c 	mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
pm_regs           762 drivers/tty/serial/mvebu-uart.c 	mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
pm_regs           763 drivers/tty/serial/mvebu-uart.c 	mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
pm_regs           775 drivers/tty/serial/mvebu-uart.c 	writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
pm_regs           776 drivers/tty/serial/mvebu-uart.c 	writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
pm_regs           777 drivers/tty/serial/mvebu-uart.c 	writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
pm_regs           778 drivers/tty/serial/mvebu-uart.c 	writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
pm_regs           779 drivers/tty/serial/mvebu-uart.c 	writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
pm_regs           780 drivers/tty/serial/mvebu-uart.c 	writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
pm_regs           781 drivers/tty/serial/mvebu-uart.c 	writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);