pm_iir 836 drivers/gpu/drm/i915/i915_debugfs.c u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; pm_iir 887 drivers/gpu/drm/i915/i915_debugfs.c pm_iir = 0; pm_iir 892 drivers/gpu/drm/i915/i915_debugfs.c pm_iir = I915_READ(GEN8_GT_IIR(2)); pm_iir 897 drivers/gpu/drm/i915/i915_debugfs.c pm_iir = I915_READ(GEN6_PMIIR); pm_iir 913 drivers/gpu/drm/i915/i915_debugfs.c pm_isr, pm_iir); pm_iir 547 drivers/gpu/drm/i915/i915_drv.h u32 pm_iir; pm_iir 346 drivers/gpu/drm/i915/i915_irq.c dev_priv->gt_pm.rps.pm_iir = 0; pm_iir 357 drivers/gpu/drm/i915/i915_irq.c dev_priv->gt_pm.rps.pm_iir = 0; pm_iir 370 drivers/gpu/drm/i915/i915_irq.c WARN_ON_ONCE(rps->pm_iir); pm_iir 1129 drivers/gpu/drm/i915/i915_irq.c static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) pm_iir 1136 drivers/gpu/drm/i915/i915_irq.c if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) pm_iir 1177 drivers/gpu/drm/i915/i915_irq.c u32 pm_iir = 0; pm_iir 1181 drivers/gpu/drm/i915/i915_irq.c pm_iir = fetch_and_zero(&rps->pm_iir); pm_iir 1187 drivers/gpu/drm/i915/i915_irq.c WARN_ON(pm_iir & ~dev_priv->pm_rps_events); pm_iir 1188 drivers/gpu/drm/i915/i915_irq.c if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) pm_iir 1193 drivers/gpu/drm/i915/i915_irq.c pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); pm_iir 1204 drivers/gpu/drm/i915/i915_irq.c } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { pm_iir 1214 drivers/gpu/drm/i915/i915_irq.c } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { pm_iir 1220 drivers/gpu/drm/i915/i915_irq.c } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { pm_iir 1658 drivers/gpu/drm/i915/i915_irq.c void gen11_rps_irq_handler(struct intel_gt *gt, u32 pm_iir) pm_iir 1662 drivers/gpu/drm/i915/i915_irq.c const u32 events = i915->pm_rps_events & pm_iir; pm_iir 1674 drivers/gpu/drm/i915/i915_irq.c rps->pm_iir |= events; pm_iir 1678 drivers/gpu/drm/i915/i915_irq.c void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) pm_iir 1683 drivers/gpu/drm/i915/i915_irq.c if (pm_iir & dev_priv->pm_rps_events) { pm_iir 1685 drivers/gpu/drm/i915/i915_irq.c gen6_gt_pm_mask_irq(gt, pm_iir & dev_priv->pm_rps_events); pm_iir 1687 drivers/gpu/drm/i915/i915_irq.c rps->pm_iir |= pm_iir & dev_priv->pm_rps_events; pm_iir 1696 drivers/gpu/drm/i915/i915_irq.c if (pm_iir & PM_VEBOX_USER_INTERRUPT) pm_iir 1699 drivers/gpu/drm/i915/i915_irq.c if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) pm_iir 1700 drivers/gpu/drm/i915/i915_irq.c DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); pm_iir 1952 drivers/gpu/drm/i915/i915_irq.c u32 iir, gt_iir, pm_iir; pm_iir 1958 drivers/gpu/drm/i915/i915_irq.c pm_iir = I915_READ(GEN6_PMIIR); pm_iir 1961 drivers/gpu/drm/i915/i915_irq.c if (gt_iir == 0 && pm_iir == 0 && iir == 0) pm_iir 1985 drivers/gpu/drm/i915/i915_irq.c if (pm_iir) pm_iir 1986 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(GEN6_PMIIR, pm_iir); pm_iir 2011 drivers/gpu/drm/i915/i915_irq.c if (pm_iir) pm_iir 2012 drivers/gpu/drm/i915/i915_irq.c gen6_rps_irq_handler(dev_priv, pm_iir); pm_iir 2538 drivers/gpu/drm/i915/i915_irq.c u32 pm_iir = I915_READ(GEN6_PMIIR); pm_iir 2539 drivers/gpu/drm/i915/i915_irq.c if (pm_iir) { pm_iir 2540 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(GEN6_PMIIR, pm_iir); pm_iir 2542 drivers/gpu/drm/i915/i915_irq.c gen6_rps_irq_handler(dev_priv, pm_iir); pm_iir 25 drivers/gpu/drm/i915/i915_irq.h void gen11_rps_irq_handler(struct intel_gt *gt, u32 pm_iir); pm_iir 26 drivers/gpu/drm/i915/i915_irq.h void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);