pm07_control       40 arch/powerpc/include/asm/cell-pmu.h #define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
pm07_control       81 arch/powerpc/include/asm/cell-regs.h 	u64	pm07_control[8];				/* 0x0440 */
pm07_control      153 arch/powerpc/include/asm/cell-regs.h 	u32 pm07_control[NR_CTRS];
pm07_control      154 arch/powerpc/platforms/cell/pmu.c 	u32 pm07_control = 0;
pm07_control      157 arch/powerpc/platforms/cell/pmu.c 		READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
pm07_control      159 arch/powerpc/platforms/cell/pmu.c 	return pm07_control;
pm07_control      166 arch/powerpc/platforms/cell/pmu.c 		WRITE_WO_MMIO(pm07_control[ctr], val);