pm07_cntrl        126 arch/powerpc/oprofile/op_model_cell.c 	u32 pm07_cntrl[NR_PHYS_CTRS];
pm07_cntrl        291 arch/powerpc/oprofile/op_model_cell.c 		pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;
pm07_cntrl        299 arch/powerpc/oprofile/op_model_cell.c 		pm_regs.pm07_cntrl[ctr] = 0;
pm07_cntrl        315 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm07_cntrl[ctr] = 0;
pm07_cntrl        316 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);
pm07_cntrl        317 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);
pm07_cntrl        318 arch/powerpc/oprofile/op_model_cell.c 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);
pm07_cntrl        343 arch/powerpc/oprofile/op_model_cell.c 		pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);
pm07_cntrl        345 arch/powerpc/oprofile/op_model_cell.c 		pm_regs.pm07_cntrl[ctr] = 0;
pm07_cntrl        424 arch/powerpc/oprofile/op_model_cell.c static inline void enable_ctr(u32 cpu, u32 ctr, u32 *pm07_cntrl)
pm07_cntrl        427 arch/powerpc/oprofile/op_model_cell.c 	pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE;
pm07_cntrl        428 arch/powerpc/oprofile/op_model_cell.c 	cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);
pm07_cntrl        535 arch/powerpc/oprofile/op_model_cell.c 					   pm_regs.pm07_cntrl);
pm07_cntrl        660 arch/powerpc/oprofile/op_model_cell.c 		enable_ctr(cpu, 0, pm_regs.pm07_cntrl);
pm07_cntrl       1366 arch/powerpc/oprofile/op_model_cell.c 			enable_ctr(cpu, 0, pm_regs.pm07_cntrl);
pm07_cntrl       1412 arch/powerpc/oprofile/op_model_cell.c 				enable_ctr(cpu, i, pm_regs.pm07_cntrl);