pllvals           121 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nvkm_pll_vals *pv = &regp->pllvals;
pllvals           603 drivers/gpu/drm/nouveau/dispnv04/dfp.c 					(&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
pllvals            40 drivers/gpu/drm/nouveau/dispnv04/disp.h 	struct nvkm_pll_vals pllvals;
pllvals           132 drivers/gpu/drm/nouveau/dispnv04/hw.c 		      uint32_t pll2, struct nvkm_pll_vals *pllvals)
pllvals           139 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pllvals->log2P = (pll1 >> 16) & 0x7;
pllvals           140 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pllvals->N2 = pllvals->M2 = 1;
pllvals           143 drivers/gpu/drm/nouveau/dispnv04/hw.c 		pllvals->NM1 = pll2 & 0xffff;
pllvals           146 drivers/gpu/drm/nouveau/dispnv04/hw.c 			pllvals->NM2 = pll2 >> 16;
pllvals           148 drivers/gpu/drm/nouveau/dispnv04/hw.c 		pllvals->NM1 = pll1 & 0xffff;
pllvals           150 drivers/gpu/drm/nouveau/dispnv04/hw.c 			pllvals->NM2 = pll2 & 0xffff;
pllvals           152 drivers/gpu/drm/nouveau/dispnv04/hw.c 			pllvals->M1 &= 0xf; /* only 4 bits */
pllvals           154 drivers/gpu/drm/nouveau/dispnv04/hw.c 				pllvals->M2 = (pll1 >> 4) & 0x7;
pllvals           155 drivers/gpu/drm/nouveau/dispnv04/hw.c 				pllvals->N2 = ((pll1 >> 21) & 0x18) |
pllvals           164 drivers/gpu/drm/nouveau/dispnv04/hw.c 		       struct nvkm_pll_vals *pllvals)
pllvals           198 drivers/gpu/drm/nouveau/dispnv04/hw.c 	nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);
pllvals           199 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pllvals->refclk = pll_lim.refclk;
pllvals           216 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nvkm_pll_vals pllvals;
pllvals           242 drivers/gpu/drm/nouveau/dispnv04/hw.c 	ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
pllvals           246 drivers/gpu/drm/nouveau/dispnv04/hw.c 	return nouveau_hw_pllvals_to_clk(&pllvals);
pllvals           401 drivers/gpu/drm/nouveau/dispnv04/hw.c 	nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
pllvals           478 drivers/gpu/drm/nouveau/dispnv04/hw.c 	clk->pll_prog(clk, pllreg, &regp->pllvals);
pllvals            44 drivers/gpu/drm/nouveau/dispnv04/hw.h 			   struct nvkm_pll_vals *pllvals);
pllvals            45 drivers/gpu/drm/nouveau/dispnv04/hw.h int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pllvals);