pllid 59 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \ pllid 60 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ pllid 82 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ pllid 83 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ pllid 108 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ pllid 109 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ pllid 474 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c #define clk_src_regs(index, pllid)\ pllid 476 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ pllid 470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c #define clk_src_regs(index, pllid)\ pllid 472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ pllid 328 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c #define clk_src_regs(index, pllid)\ pllid 330 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c CS_COMMON_REG_LIST_DCN2_1(index, pllid),\