pllctrl           158 drivers/clk/keystone/pll.c static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
pllctrl           197 drivers/clk/keystone/pll.c 	pll_data->has_pllctrl = pllctrl;
pllctrl           447 drivers/gpu/drm/bridge/tc358767.c static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
pllctrl           451 drivers/gpu/drm/bridge/tc358767.c 	ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
pllctrl            79 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	u32 val, tmdsck, idf, odf, pllctrl = 0;
pllctrl           103 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	pllctrl |= 40 << PLL_CFG_NDIV_SHIFT;
pllctrl           110 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	pllctrl |= idf << PLL_CFG_IDF_SHIFT;
pllctrl           111 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	pllctrl |= odf << PLL_CFG_ODF_SHIFT;
pllctrl           117 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl);
pllctrl           118 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG);