pllc              402 arch/powerpc/boot/4xx.c 	u32 pllc  = CPR0_READ(DCRN_CPR0_PLLC);
pllc              424 arch/powerpc/boot/4xx.c 	if (pllc & 0x40000000) {
pllc              428 arch/powerpc/boot/4xx.c 		switch ((pllc >> 24) & 7) {
pllc              431 arch/powerpc/boot/4xx.c 			m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
pllc              726 arch/powerpc/boot/4xx.c 	u32 pllc  = CPR0_READ(DCRN_CPR0_PLLC);
pllc              752 arch/powerpc/boot/4xx.c 	if (pllc & 0x40000000) {
pllc              756 arch/powerpc/boot/4xx.c 		switch ((pllc >> 24) & 7) {