pll_regs 141 drivers/clk/mvebu/ap-cpu-clk.c const struct cpu_dfs_regs *pll_regs; pll_regs 151 drivers/clk/mvebu/ap-cpu-clk.c cpu_clkdiv_reg = clk->pll_regs->divider_reg + pll_regs 152 drivers/clk/mvebu/ap-cpu-clk.c (clk->cluster * clk->pll_regs->cluster_offset); pll_regs 154 drivers/clk/mvebu/ap-cpu-clk.c cpu_clkdiv_ratio &= clk->pll_regs->divider_mask; pll_regs 155 drivers/clk/mvebu/ap-cpu-clk.c cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset; pll_regs 167 drivers/clk/mvebu/ap-cpu-clk.c cpu_clkdiv_reg = clk->pll_regs->divider_reg + pll_regs 168 drivers/clk/mvebu/ap-cpu-clk.c (clk->cluster * clk->pll_regs->cluster_offset); pll_regs 169 drivers/clk/mvebu/ap-cpu-clk.c cpu_force_reg = clk->pll_regs->force_reg + pll_regs 170 drivers/clk/mvebu/ap-cpu-clk.c (clk->cluster * clk->pll_regs->cluster_offset); pll_regs 171 drivers/clk/mvebu/ap-cpu-clk.c cpu_ratio_reg = clk->pll_regs->ratio_reg + pll_regs 172 drivers/clk/mvebu/ap-cpu-clk.c (clk->cluster * clk->pll_regs->cluster_offset); pll_regs 175 drivers/clk/mvebu/ap-cpu-clk.c reg &= ~(clk->pll_regs->divider_mask); pll_regs 176 drivers/clk/mvebu/ap-cpu-clk.c reg |= (divider << clk->pll_regs->divider_offset); pll_regs 182 drivers/clk/mvebu/ap-cpu-clk.c if (clk->pll_regs->divider_ratio) { pll_regs 184 drivers/clk/mvebu/ap-cpu-clk.c reg |= ((divider * clk->pll_regs->divider_ratio) << pll_regs 191 drivers/clk/mvebu/ap-cpu-clk.c clk->pll_regs->force_mask, pll_regs 192 drivers/clk/mvebu/ap-cpu-clk.c clk->pll_regs->force_mask); pll_regs 195 drivers/clk/mvebu/ap-cpu-clk.c BIT(clk->pll_regs->ratio_offset), pll_regs 196 drivers/clk/mvebu/ap-cpu-clk.c BIT(clk->pll_regs->ratio_offset)); pll_regs 198 drivers/clk/mvebu/ap-cpu-clk.c stable_bit = BIT(clk->pll_regs->ratio_state_offset + pll_regs 200 drivers/clk/mvebu/ap-cpu-clk.c clk->pll_regs->ratio_state_cluster_offset), pll_regs 202 drivers/clk/mvebu/ap-cpu-clk.c clk->pll_regs->ratio_state_reg, reg, pll_regs 209 drivers/clk/mvebu/ap-cpu-clk.c BIT(clk->pll_regs->ratio_offset), 0); pll_regs 314 drivers/clk/mvebu/ap-cpu-clk.c ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev); pll_regs 1151 drivers/clk/sunxi-ng/ccu-sun50i-h6.c static const u32 pll_regs[] = { pll_regs 1188 drivers/clk/sunxi-ng/ccu-sun50i-h6.c for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { pll_regs 1189 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + pll_regs[i]); pll_regs 1191 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel(val, reg + pll_regs[i]); pll_regs 955 drivers/media/i2c/ov2659.c struct sensor_register pll_regs[] = { pll_regs 964 drivers/media/i2c/ov2659.c return ov2659_write_array(client, pll_regs); pll_regs 3037 drivers/video/fbdev/aty/atyfb_base.c u8 pll_regs[16]; pll_regs 3060 drivers/video/fbdev/aty/atyfb_base.c pll_regs[i] = aty_ld_pll_ct(i, par); pll_regs 3065 drivers/video/fbdev/aty/atyfb_base.c M = pll_regs[PLL_REF_DIV]; pll_regs 3070 drivers/video/fbdev/aty/atyfb_base.c N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)]; pll_regs 3075 drivers/video/fbdev/aty/atyfb_base.c P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) | pll_regs 3076 drivers/video/fbdev/aty/atyfb_base.c ((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)]; pll_regs 1257 sound/soc/codecs/adau1373.c uint8_t pll_regs[5]; pll_regs 1299 sound/soc/codecs/adau1373.c ret = adau_calc_pll_cfg(freq_in, freq_out, pll_regs); pll_regs 1315 sound/soc/codecs/adau1373.c regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), pll_regs[0]); pll_regs 1316 sound/soc/codecs/adau1373.c regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), pll_regs[1]); pll_regs 1317 sound/soc/codecs/adau1373.c regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), pll_regs[2]); pll_regs 1318 sound/soc/codecs/adau1373.c regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), pll_regs[3]); pll_regs 1319 sound/soc/codecs/adau1373.c regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), pll_regs[4]); pll_regs 79 sound/soc/codecs/adau17x1.c adau->pll_regs[5] = 1; pll_regs 81 sound/soc/codecs/adau17x1.c adau->pll_regs[5] = 0; pll_regs 90 sound/soc/codecs/adau17x1.c adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); pll_regs 358 sound/soc/codecs/adau17x1.c ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs); pll_regs 364 sound/soc/codecs/adau17x1.c adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); pll_regs 1057 sound/soc/codecs/adau17x1.c adau->pll_regs); pll_regs 45 sound/soc/codecs/adau17x1.h uint8_t pll_regs[6];