pll_ref_div        28 drivers/clk/tegra/clk-tegra-fixed.c 	u32 val, pll_ref_div;
pll_ref_div        56 drivers/clk/tegra/clk-tegra-fixed.c 	pll_ref_div = 1 << val;
pll_ref_div        62 drivers/clk/tegra/clk-tegra-fixed.c 					0, 1, pll_ref_div);
pll_ref_div        66 drivers/clk/tegra/clk-tegra-fixed.c 		*pll_ref_freq = *osc_freq / pll_ref_div;
pll_ref_div       576 drivers/clk/tegra/clk-tegra20.c 	u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
pll_ref_div       581 drivers/clk/tegra/clk-tegra20.c 		BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
pll_ref_div       585 drivers/clk/tegra/clk-tegra20.c 		BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
pll_ref_div       589 drivers/clk/tegra/clk-tegra20.c 		BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
pll_ref_div       593 drivers/clk/tegra/clk-tegra20.c 		BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
pll_ref_div       608 drivers/clk/tegra/clk-tegra20.c 	u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
pll_ref_div       611 drivers/clk/tegra/clk-tegra20.c 	switch (pll_ref_div) {
pll_ref_div       619 drivers/clk/tegra/clk-tegra20.c 		pr_err("Invalid pll ref divider %d\n", pll_ref_div);
pll_ref_div       895 drivers/clk/tegra/clk-tegra20.c 	unsigned int pll_ref_div;
pll_ref_div       905 drivers/clk/tegra/clk-tegra20.c 	pll_ref_div = tegra20_get_pll_ref_div();
pll_ref_div       907 drivers/clk/tegra/clk-tegra20.c 					CLK_SET_RATE_PARENT, 1, pll_ref_div);
pll_ref_div       747 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 	uint32_t pll_ref_div = 0;
pll_ref_div       802 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 							pll_ref_div = lvds->panel_ref_divider;
pll_ref_div       836 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 		pll_ref_div   = reference_div;
pll_ref_div       850 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 					   pll_ref_div & 0x3ff,
pll_ref_div       860 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 						     &pll_ref_div, &pll_fb_post_div,
pll_ref_div       877 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			     pll_ref_div,
pll_ref_div       900 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			  (unsigned)pll_ref_div,
pll_ref_div       905 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			  (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
pll_ref_div       923 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
pll_ref_div       934 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
pll_ref_div       967 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
pll_ref_div       972 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 					     pll_ref_div,
pll_ref_div       977 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 					     (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
pll_ref_div       982 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 				     pll_ref_div,
pll_ref_div      1006 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			  pll_ref_div,
pll_ref_div      1011 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			  pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
pll_ref_div        83 drivers/video/fbdev/aty/atyfb.h 	u8 pll_ref_div;
pll_ref_div      1791 drivers/video/fbdev/aty/atyfb_base.c 	u8 pll_ref_div;
pll_ref_div      1849 drivers/video/fbdev/aty/atyfb_base.c 			clk.pll_ref_div = pll->ct.pll_ref_div;
pll_ref_div      1875 drivers/video/fbdev/aty/atyfb_base.c 			pll->ct.pll_ref_div = clk.pll_ref_div;
pll_ref_div      2435 drivers/video/fbdev/aty/atyfb_base.c 		u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
pll_ref_div      2437 drivers/video/fbdev/aty/atyfb_base.c 		if (pll_ref_div) {
pll_ref_div      2439 drivers/video/fbdev/aty/atyfb_base.c 			diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
pll_ref_div      2440 drivers/video/fbdev/aty/atyfb_base.c 			diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
pll_ref_div       216 drivers/video/fbdev/aty/mach64_ct.c 	q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
pll_ref_div       229 drivers/video/fbdev/aty/mach64_ct.c 		(par->ref_clk_per * pll->pll_ref_div);
pll_ref_div       268 drivers/video/fbdev/aty/mach64_ct.c 	ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
pll_ref_div       297 drivers/video/fbdev/aty/mach64_ct.c 		pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
pll_ref_div       388 drivers/video/fbdev/aty/mach64_ct.c 	pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
pll_ref_div       514 drivers/video/fbdev/aty/mach64_ct.c 		pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
pll_ref_div       524 drivers/video/fbdev/aty/mach64_ct.c 	pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
pll_ref_div       527 drivers/video/fbdev/aty/mach64_ct.c 	q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
pll_ref_div       551 drivers/video/fbdev/aty/mach64_ct.c 			(par->ref_clk_per * pll->ct.pll_ref_div);
pll_ref_div       578 drivers/video/fbdev/aty/mach64_ct.c 		q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
pll_ref_div       592 drivers/video/fbdev/aty/mach64_ct.c 			(par->ref_clk_per * pll->ct.pll_ref_div);
pll_ref_div       627 drivers/video/fbdev/aty/mach64_ct.c 	aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
pll_ref_div      1164 drivers/video/fbdev/w100fb.c 	w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M;
pll_ref_div      1235 drivers/video/fbdev/w100fb.c 	w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = 0x0;     /* M = 1 */
pll_ref_div       661 drivers/video/fbdev/w100fb.h 	u32 pll_ref_div      : 4;