pll_postdiv       107 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	u32 pll_postdiv;
pll_postdiv       562 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1;
pll_postdiv       600 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV;
pll_postdiv       912 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm_postdiv *pll_postdiv;
pll_postdiv       923 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL);
pll_postdiv       924 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	if (!pll_postdiv)
pll_postdiv       927 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_postdiv->pll = pll_14nm;
pll_postdiv       928 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_postdiv->shift = shift;
pll_postdiv       930 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_postdiv->width = 4;
pll_postdiv       932 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
pll_postdiv       933 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_postdiv->hw.init = &postdiv_init;
pll_postdiv       935 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	ret = clk_hw_register(dev, &pll_postdiv->hw);
pll_postdiv       939 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	return &pll_postdiv->hw;