pll_post_div      230 arch/mips/netlogic/xlp/nlm_hal.c 	unsigned int pll_post_div, ctrl_val0, ctrl_val1, denom;
pll_post_div      250 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 2;
pll_post_div      253 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 4;
pll_post_div      256 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 8;
pll_post_div      259 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 16;
pll_post_div      263 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 1;
pll_post_div      268 arch/mips/netlogic/xlp/nlm_hal.c 	denom = 3 * pll_post_div;
pll_post_div      310 arch/mips/netlogic/xlp/nlm_hal.c 	u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div, cpu_xlp9xx;
pll_post_div      406 arch/mips/netlogic/xlp/nlm_hal.c 	pll_post_div = (ctrl_val0 >> 24) & 0x7;
pll_post_div      411 arch/mips/netlogic/xlp/nlm_hal.c 	switch (pll_post_div) {
pll_post_div      413 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 2;
pll_post_div      416 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 4;
pll_post_div      419 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 8;
pll_post_div      422 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 16;
pll_post_div      426 arch/mips/netlogic/xlp/nlm_hal.c 		pll_post_div = 1;
pll_post_div      432 arch/mips/netlogic/xlp/nlm_hal.c 	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div;
pll_post_div      414 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 	u32 pll_post_div;
pll_post_div      442 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c 				amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
pll_post_div      852 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c 	pll->post_div = amdgpu_crtc->pll_post_div;
pll_post_div      746 drivers/gpu/drm/radeon/atombios_crtc.c 					radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
pll_post_div     1099 drivers/gpu/drm/radeon/atombios_crtc.c 	pll->post_div = radeon_crtc->pll_post_div;
pll_post_div      363 drivers/gpu/drm/radeon/radeon_mode.h 	u32 pll_post_div;