pll_phy_clock     527 drivers/gpu/drm/vc4/vc4_dsi.c 	struct clk *pll_phy_clock;
pll_phy_clock     759 drivers/gpu/drm/vc4/vc4_dsi.c 	clk_disable_unprepare(dsi->pll_phy_clock);
pll_phy_clock     785 drivers/gpu/drm/vc4/vc4_dsi.c 	struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
pll_phy_clock     851 drivers/gpu/drm/vc4/vc4_dsi.c 	ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
pll_phy_clock     918 drivers/gpu/drm/vc4/vc4_dsi.c 	ret = clk_prepare_enable(dsi->pll_phy_clock);
pll_phy_clock     924 drivers/gpu/drm/vc4/vc4_dsi.c 	hs_clock = clk_get_rate(dsi->pll_phy_clock);
pll_phy_clock    1381 drivers/gpu/drm/vc4/vc4_dsi.c 	const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
pll_phy_clock    1546 drivers/gpu/drm/vc4/vc4_dsi.c 	dsi->pll_phy_clock = devm_clk_get(dev, "phy");
pll_phy_clock    1547 drivers/gpu/drm/vc4/vc4_dsi.c 	if (IS_ERR(dsi->pll_phy_clock)) {
pll_phy_clock    1548 drivers/gpu/drm/vc4/vc4_dsi.c 		ret = PTR_ERR(dsi->pll_phy_clock);