pll_mux_ops        29 drivers/clk/rockchip/clk-pll.c 	const struct clk_ops	*pll_mux_ops;
pll_mux_ops       181 drivers/clk/rockchip/clk-pll.c 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
pll_mux_ops       196 drivers/clk/rockchip/clk-pll.c 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
pll_mux_ops       198 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
pll_mux_ops       232 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
pll_mux_ops       414 drivers/clk/rockchip/clk-pll.c 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
pll_mux_ops       427 drivers/clk/rockchip/clk-pll.c 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
pll_mux_ops       429 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
pll_mux_ops       465 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
pll_mux_ops       658 drivers/clk/rockchip/clk-pll.c 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
pll_mux_ops       673 drivers/clk/rockchip/clk-pll.c 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
pll_mux_ops       675 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
pll_mux_ops       711 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
pll_mux_ops       860 drivers/clk/rockchip/clk-pll.c 	pll->pll_mux_ops = &clk_mux_ops;
pll_mux_ops       885 drivers/clk/rockchip/clk-pll.c 	init.ops = pll->pll_mux_ops;