pll_mux            28 drivers/clk/rockchip/clk-pll.c 	struct clk_mux		pll_mux;
pll_mux           182 drivers/clk/rockchip/clk-pll.c 	struct clk_mux *pll_mux = &pll->pll_mux;
pll_mux           196 drivers/clk/rockchip/clk-pll.c 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
pll_mux           198 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
pll_mux           232 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
pll_mux           415 drivers/clk/rockchip/clk-pll.c 	struct clk_mux *pll_mux = &pll->pll_mux;
pll_mux           427 drivers/clk/rockchip/clk-pll.c 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
pll_mux           429 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
pll_mux           465 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
pll_mux           659 drivers/clk/rockchip/clk-pll.c 	struct clk_mux *pll_mux = &pll->pll_mux;
pll_mux           673 drivers/clk/rockchip/clk-pll.c 	cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
pll_mux           675 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
pll_mux           711 drivers/clk/rockchip/clk-pll.c 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
pll_mux           842 drivers/clk/rockchip/clk-pll.c 	struct clk_mux *pll_mux;
pll_mux           861 drivers/clk/rockchip/clk-pll.c 	pll_mux = &pll->pll_mux;
pll_mux           862 drivers/clk/rockchip/clk-pll.c 	pll_mux->reg = ctx->reg_base + mode_offset;
pll_mux           863 drivers/clk/rockchip/clk-pll.c 	pll_mux->shift = mode_shift;
pll_mux           865 drivers/clk/rockchip/clk-pll.c 		pll_mux->mask = PLL_RK3328_MODE_MASK;
pll_mux           867 drivers/clk/rockchip/clk-pll.c 		pll_mux->mask = PLL_MODE_MASK;
pll_mux           868 drivers/clk/rockchip/clk-pll.c 	pll_mux->flags = 0;
pll_mux           869 drivers/clk/rockchip/clk-pll.c 	pll_mux->lock = &ctx->lock;
pll_mux           870 drivers/clk/rockchip/clk-pll.c 	pll_mux->hw.init = &init;
pll_mux           876 drivers/clk/rockchip/clk-pll.c 		pll_mux->flags |= CLK_MUX_HIWORD_MASK;
pll_mux           892 drivers/clk/rockchip/clk-pll.c 	mux_clk = clk_register(NULL, &pll_mux->hw);
pll_mux            15 drivers/clk/socfpga/clk-s10.c static const char * const pll_mux[] = { "osc1", "cb-intosc-hs-div2-clk",
pll_mux            49 drivers/clk/socfpga/clk-s10.c 	{ STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
pll_mux            51 drivers/clk/socfpga/clk-s10.c 	{ STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
pll_mux            84 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	u8 pll_mux;
pll_mux           549 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	cached->pll_mux = cmn_clk_cfg1 & 0x3;
pll_mux           553 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	    cached->pix_clk_div, cached->pll_mux);
pll_mux           573 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	val |= cached->pll_mux;