pll_lim           122 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nvbios_pll pll_lim;
pll_lim           125 drivers/gpu/drm/nouveau/dispnv04/crtc.c 			    &pll_lim))
pll_lim           141 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
pll_lim           142 drivers/gpu/drm/nouveau/dispnv04/crtc.c 		memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
pll_lim           145 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
pll_lim           170 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nvbios_pll pll_lim;
pll_lim           173 drivers/gpu/drm/nouveau/dispnv04/hw.c 	ret = nvbios_pll_parse(bios, plltype, &pll_lim);
pll_lim           174 drivers/gpu/drm/nouveau/dispnv04/hw.c 	if (ret || !(reg1 = pll_lim.reg))
pll_lim           199 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pllvals->refclk = pll_lim.refclk;
pll_lim           262 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nvbios_pll pll_lim;
pll_lim           266 drivers/gpu/drm/nouveau/dispnv04/hw.c 	if (nvbios_pll_parse(bios, pll, &pll_lim))
pll_lim           270 drivers/gpu/drm/nouveau/dispnv04/hw.c 	if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
pll_lim           271 drivers/gpu/drm/nouveau/dispnv04/hw.c 	    pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
pll_lim           272 drivers/gpu/drm/nouveau/dispnv04/hw.c 	    pv.log2P <= pll_lim.max_p)
pll_lim           278 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pv.M1 = pll_lim.vco1.max_m;
pll_lim           279 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pv.N1 = pll_lim.vco1.min_n;
pll_lim           280 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pv.log2P = pll_lim.max_p_usable;
pll_lim           281 drivers/gpu/drm/nouveau/dispnv04/hw.c 	clk->pll_prog(clk, pll_lim.reg, &pv);