pll_ctl_val       832 arch/arm/mach-omap1/clock_data.c 		unsigned pll_ctl_val = omap_readw(DPLL_CTL);
pll_ctl_val       835 arch/arm/mach-omap1/clock_data.c 		if (pll_ctl_val & 0x10) {
pll_ctl_val       837 arch/arm/mach-omap1/clock_data.c 			if (pll_ctl_val & 0xf80)
pll_ctl_val       838 arch/arm/mach-omap1/clock_data.c 				ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
pll_ctl_val       839 arch/arm/mach-omap1/clock_data.c 			ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
pll_ctl_val       842 arch/arm/mach-omap1/clock_data.c 			switch (pll_ctl_val & 0xc) {