pll_clock_khz 516 drivers/ata/pata_pdc2027x.c long pll_clock_khz = pll_clock / 1000; pll_clock_khz 518 drivers/ata/pata_pdc2027x.c long ratio = pout_required / pll_clock_khz; pll_clock_khz 522 drivers/ata/pata_pdc2027x.c if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) { pll_clock_khz 523 drivers/ata/pata_pdc2027x.c printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);