pll_base_freq     362 drivers/gpu/drm/meson/meson_vclk.c 	unsigned int pll_base_freq;
pll_base_freq     371 drivers/gpu/drm/meson/meson_vclk.c 		.pll_base_freq = 4320000,
pll_base_freq     380 drivers/gpu/drm/meson/meson_vclk.c 		.pll_base_freq = 4320000,
pll_base_freq     389 drivers/gpu/drm/meson/meson_vclk.c 		.pll_base_freq = 2970000,
pll_base_freq     398 drivers/gpu/drm/meson/meson_vclk.c 		.pll_base_freq = 2970000,
pll_base_freq     407 drivers/gpu/drm/meson/meson_vclk.c 		.pll_base_freq = 2970000,
pll_base_freq     416 drivers/gpu/drm/meson/meson_vclk.c 		.pll_base_freq = 5940000,
pll_base_freq     425 drivers/gpu/drm/meson/meson_vclk.c 		.pll_base_freq = 5940000,
pll_base_freq     748 drivers/gpu/drm/meson/meson_vclk.c static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
pll_base_freq     766 drivers/gpu/drm/meson/meson_vclk.c 		meson_hdmi_pll_generic_set(priv, pll_base_freq);
pll_base_freq     768 drivers/gpu/drm/meson/meson_vclk.c 		switch (pll_base_freq) {
pll_base_freq     786 drivers/gpu/drm/meson/meson_vclk.c 		switch (pll_base_freq) {
pll_base_freq     803 drivers/gpu/drm/meson/meson_vclk.c 		switch (pll_base_freq) {
pll_base_freq    1042 drivers/gpu/drm/meson/meson_vclk.c 	meson_vclk_set(priv, params[freq].pll_base_freq,