pll_base           93 arch/mips/ath79/clock.c static void __init ar71xx_clocks_init(void __iomem *pll_base)
pll_base          105 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
pll_base          124 arch/mips/ath79/clock.c static void __init ar724x_clocks_init(void __iomem *pll_base)
pll_base          131 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
pll_base          144 arch/mips/ath79/clock.c static void __init ar933x_clocks_init(void __iomem *pll_base)
pll_base          165 arch/mips/ath79/clock.c 	clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
pll_base          178 arch/mips/ath79/clock.c 		cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
pll_base          232 arch/mips/ath79/clock.c static void __init ar934x_clocks_init(void __iomem *pll_base)
pll_base          265 arch/mips/ath79/clock.c 		pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
pll_base          292 arch/mips/ath79/clock.c 		pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
pll_base          307 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
pll_base          343 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
pll_base          350 arch/mips/ath79/clock.c static void __init qca953x_clocks_init(void __iomem *pll_base)
pll_base          368 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
pll_base          382 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
pll_base          396 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
pll_base          433 arch/mips/ath79/clock.c static void __init qca955x_clocks_init(void __iomem *pll_base)
pll_base          451 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
pll_base          465 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
pll_base          479 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
pll_base          516 arch/mips/ath79/clock.c static void __init qca956x_clocks_init(void __iomem *pll_base)
pll_base          544 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
pll_base          550 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
pll_base          563 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
pll_base          568 arch/mips/ath79/clock.c 	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
pll_base          581 arch/mips/ath79/clock.c 	clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
pll_base          621 arch/mips/ath79/clock.c 	void __iomem *pll_base;
pll_base          627 arch/mips/ath79/clock.c 	pll_base = of_iomap(np, 0);
pll_base          628 arch/mips/ath79/clock.c 	if (!pll_base) {
pll_base          634 arch/mips/ath79/clock.c 		ar71xx_clocks_init(pll_base);
pll_base          637 arch/mips/ath79/clock.c 		ar724x_clocks_init(pll_base);
pll_base          639 arch/mips/ath79/clock.c 		ar933x_clocks_init(pll_base);
pll_base          641 arch/mips/ath79/clock.c 		ar934x_clocks_init(pll_base);
pll_base          643 arch/mips/ath79/clock.c 		qca953x_clocks_init(pll_base);
pll_base          645 arch/mips/ath79/clock.c 		qca955x_clocks_init(pll_base);
pll_base          647 arch/mips/ath79/clock.c 		qca956x_clocks_init(pll_base);
pll_base          660 arch/mips/ath79/clock.c 	iounmap(pll_base);
pll_base          307 drivers/clk/imx/clk-imx5.c 	void __iomem *pll_base;
pll_base          310 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
pll_base          311 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          312 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);
pll_base          314 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
pll_base          315 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          316 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);
pll_base          318 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
pll_base          319 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          320 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);
pll_base          392 drivers/clk/imx/clk-imx5.c 	void __iomem *pll_base;
pll_base          395 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
pll_base          396 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          397 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);
pll_base          399 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
pll_base          400 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          401 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);
pll_base          403 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
pll_base          404 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          405 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);
pll_base          498 drivers/clk/imx/clk-imx5.c 	void __iomem *pll_base;
pll_base          501 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
pll_base          502 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          503 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);
pll_base          505 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
pll_base          506 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          507 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);
pll_base          509 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
pll_base          510 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          511 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);
pll_base          513 drivers/clk/imx/clk-imx5.c 	pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
pll_base          514 drivers/clk/imx/clk-imx5.c 	WARN_ON(!pll_base);
pll_base          515 drivers/clk/imx/clk-imx5.c 	clk[IMX5_CLK_PLL4_SW]		= imx_clk_pllv2("pll4_sw", "osc", pll_base);
pll_base          693 drivers/clk/st/clkgen-pll.c 	void __iomem *pll_base;
pll_base          703 drivers/clk/st/clkgen-pll.c 	pll_base = clkgen_get_register_base(np);
pll_base          704 drivers/clk/st/clkgen-pll.c 	if (!pll_base)
pll_base          709 drivers/clk/st/clkgen-pll.c 	clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
pll_base          740 drivers/clk/st/clkgen-pll.c 		clk = clkgen_odf_register(pll_name, pll_base, data, odf_flags,
pll_base          323 drivers/gpu/drm/omapdrm/dss/dsi.c 	void __iomem *pll_base;
pll_base          443 drivers/gpu/drm/omapdrm/dss/dsi.c 		case DSI_PLL: base = dsi->pll_base; break;
pll_base          457 drivers/gpu/drm/omapdrm/dss/dsi.c 		case DSI_PLL: base = dsi->pll_base; break;
pll_base         5030 drivers/gpu/drm/omapdrm/dss/dsi.c 	pll->base = dsi->pll_base;
pll_base         5310 drivers/gpu/drm/omapdrm/dss/dsi.c 	dsi->pll_base = devm_ioremap_resource(dev, res);
pll_base         5311 drivers/gpu/drm/omapdrm/dss/dsi.c 	if (IS_ERR(dsi->pll_base))
pll_base         5312 drivers/gpu/drm/omapdrm/dss/dsi.c 		return PTR_ERR(dsi->pll_base);
pll_base          142 drivers/gpu/drm/omapdrm/dss/video-pll.c 	void __iomem *pll_base, *clkctrl_base;
pll_base          150 drivers/gpu/drm/omapdrm/dss/video-pll.c 	pll_base = devm_ioremap_resource(&pdev->dev, res);
pll_base          151 drivers/gpu/drm/omapdrm/dss/video-pll.c 	if (IS_ERR(pll_base))
pll_base          152 drivers/gpu/drm/omapdrm/dss/video-pll.c 		return ERR_CAST(pll_base);
pll_base          183 drivers/gpu/drm/omapdrm/dss/video-pll.c 	pll->base = pll_base;
pll_base          294 drivers/video/fbdev/omap2/omapfb/dss/dsi.c 	void __iomem *pll_base;
pll_base          440 drivers/video/fbdev/omap2/omapfb/dss/dsi.c 		case DSI_PLL: base = dsi->pll_base; break;
pll_base          456 drivers/video/fbdev/omap2/omapfb/dss/dsi.c 		case DSI_PLL: base = dsi->pll_base; break;
pll_base         5223 drivers/video/fbdev/omap2/omapfb/dss/dsi.c 	pll->base = dsi->pll_base;
pll_base         5348 drivers/video/fbdev/omap2/omapfb/dss/dsi.c 	dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
pll_base         5350 drivers/video/fbdev/omap2/omapfb/dss/dsi.c 	if (!dsi->pll_base) {
pll_base          134 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c 	void __iomem *pll_base, *clkctrl_base;
pll_base          148 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c 	pll_base = devm_ioremap_resource(&pdev->dev, res);
pll_base          149 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c 	if (IS_ERR(pll_base)) {
pll_base          151 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c 		return ERR_CAST(pll_base);
pll_base          191 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c 	pll->base = pll_base;