pll_28nm 91 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, pll_28nm 98 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); pll_28nm 111 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) pll_28nm 113 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; pll_28nm 131 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 132 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct device *dev = &pll_28nm->pdev->dev; pll_28nm 133 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; pll_28nm 224 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c if (pll_28nm->vco_delay) pll_28nm 225 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c udelay(pll_28nm->vco_delay); pll_28nm 246 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 248 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, pll_28nm 256 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 257 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; pll_28nm 315 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 316 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct device *dev = &pll_28nm->pdev->dev; pll_28nm 317 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; pll_28nm 323 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c DBG("id=%d", pll_28nm->id); pll_28nm 325 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm_software_reset(pll_28nm); pll_28nm 350 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c locked = pll_28nm_poll_for_ready(pll_28nm, pll_28nm 355 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm_software_reset(pll_28nm); pll_28nm 390 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 391 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct device *dev = &pll_28nm->pdev->dev; pll_28nm 392 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; pll_28nm 397 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c DBG("id=%d", pll_28nm->id); pll_28nm 399 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm_software_reset(pll_28nm); pll_28nm 421 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); pll_28nm 433 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 435 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c DBG("id=%d", pll_28nm->id); pll_28nm 436 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); pll_28nm 441 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 442 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; pll_28nm 443 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; pll_28nm 455 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 456 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; pll_28nm 457 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; pll_28nm 463 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c DRM_DEV_ERROR(&pll_28nm->pdev->dev, pll_28nm 482 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 485 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; pll_28nm 488 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; pll_28nm 495 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 498 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, pll_28nm 499 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->clks, pll_28nm->num_clks); pll_28nm 502 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->provided_clks[i] = NULL; pll_28nm 504 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->num_clks = 0; pll_28nm 505 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->clk_data.clks = NULL; pll_28nm 506 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->clk_data.clk_num = 0; pll_28nm 509 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) pll_28nm 519 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct device *dev = &pll_28nm->pdev->dev; pll_28nm 520 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct clk **clks = pll_28nm->clks; pll_28nm 521 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct clk **provided_clks = pll_28nm->provided_clks; pll_28nm 525 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c DBG("%d", pll_28nm->id); pll_28nm 527 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); pll_28nm 528 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->base.clk_hw.init = &vco_init; pll_28nm 529 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); pll_28nm 531 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); pll_28nm 532 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); pll_28nm 535 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->mmio + pll_28nm 539 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); pll_28nm 540 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); pll_28nm 545 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); pll_28nm 546 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); pll_28nm 549 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c parent1, 0, pll_28nm->mmio + pll_28nm 553 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id); pll_28nm 554 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); pll_28nm 555 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); pll_28nm 559 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c }, 2, CLK_SET_RATE_PARENT, pll_28nm->mmio + pll_28nm 562 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); pll_28nm 563 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id); pll_28nm 568 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->num_clks = num; pll_28nm 570 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; pll_28nm 571 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->clk_data.clks = provided_clks; pll_28nm 574 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c of_clk_src_onecell_get, &pll_28nm->clk_data); pll_28nm 586 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm; pll_28nm 593 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); pll_28nm 594 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c if (!pll_28nm) pll_28nm 597 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->pdev = pdev; pll_28nm 598 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->id = id; pll_28nm 600 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); pll_28nm 601 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c if (IS_ERR_OR_NULL(pll_28nm->mmio)) { pll_28nm 606 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll = &pll_28nm->base; pll_28nm 616 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->vco_delay = 1; pll_28nm 623 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->vco_delay = 1000; pll_28nm 632 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c ret = pll_28nm_register(pll_28nm); pll_28nm 86 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, pll_28nm 93 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); pll_28nm 113 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 114 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; pll_28nm 154 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 156 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, pll_28nm 164 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 165 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; pll_28nm 289 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 290 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct device *dev = &pll_28nm->pdev->dev; pll_28nm 291 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; pll_28nm 297 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c DBG("id=%d", pll_28nm->id); pll_28nm 319 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); pll_28nm 331 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 333 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c DBG("id=%d", pll_28nm->id); pll_28nm 334 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); pll_28nm 339 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 340 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; pll_28nm 341 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; pll_28nm 355 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 356 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; pll_28nm 357 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; pll_28nm 363 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c DRM_DEV_ERROR(&pll_28nm->pdev->dev, pll_28nm 382 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 385 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; pll_28nm 388 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; pll_28nm 395 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll_28nm 397 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, pll_28nm 398 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->clks, pll_28nm->num_clks); pll_28nm 401 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) pll_28nm 410 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct device *dev = &pll_28nm->pdev->dev; pll_28nm 411 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct clk **clks = pll_28nm->clks; pll_28nm 412 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct clk **provided_clks = pll_28nm->provided_clks; pll_28nm 417 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c DBG("%d", pll_28nm->id); pll_28nm 435 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->bytediv = bytediv; pll_28nm 437 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); pll_28nm 440 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->base.clk_hw.init = &vco_init; pll_28nm 442 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); pll_28nm 446 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; pll_28nm 448 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->id); pll_28nm 449 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); pll_28nm 461 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); pll_28nm 465 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c parent_name, 0, pll_28nm->mmio + pll_28nm 469 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->num_clks = num; pll_28nm 471 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; pll_28nm 472 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->clk_data.clks = provided_clks; pll_28nm 475 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c of_clk_src_onecell_get, &pll_28nm->clk_data); pll_28nm 487 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm; pll_28nm 494 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); pll_28nm 495 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c if (!pll_28nm) pll_28nm 498 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->pdev = pdev; pll_28nm 499 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->id = id + 1; pll_28nm 501 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); pll_28nm 502 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c if (IS_ERR_OR_NULL(pll_28nm->mmio)) { pll_28nm 507 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll = &pll_28nm->base; pll_28nm 519 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c ret = pll_28nm_register(pll_28nm);