pll_14nm          176 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
pll_14nm          180 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *base = pll_14nm->mmio;
pll_14nm          489 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
pll_14nm          491 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
pll_14nm          578 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
pll_14nm          579 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_input *pin = &pll_14nm->in;
pll_14nm          580 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_output *pout = &pll_14nm->out;
pll_14nm          582 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate,
pll_14nm          585 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->vco_current_rate = rate;
pll_14nm          586 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
pll_14nm          588 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	dsi_pll_14nm_input_init(pll_14nm);
pll_14nm          602 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm_dec_frac_calc(pll_14nm);
pll_14nm          605 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 		pll_14nm_ssc_calc(pll_14nm);
pll_14nm          607 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm_calc_vco_count(pll_14nm);
pll_14nm          613 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
pll_14nm          614 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
pll_14nm          619 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_db_commit_14nm(pll_14nm, pin, pout);
pll_14nm          628 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
pll_14nm          629 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *base = pll_14nm->mmio;
pll_14nm          681 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = postdiv->pll;
pll_14nm          682 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *base = pll_14nm->phy_cmn_mmio;
pll_14nm          687 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate);
pll_14nm          701 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = postdiv->pll;
pll_14nm          703 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate);
pll_14nm          714 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = postdiv->pll;
pll_14nm          715 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *base = pll_14nm->phy_cmn_mmio;
pll_14nm          716 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	spinlock_t *lock = &pll_14nm->postdiv_lock;
pll_14nm          723 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate,
pll_14nm          740 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
pll_14nm          741 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
pll_14nm          764 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
pll_14nm          765 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *base = pll_14nm->mmio;
pll_14nm          766 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
pll_14nm          774 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
pll_14nm          778 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 		DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
pll_14nm          787 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
pll_14nm          788 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
pll_14nm          797 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
pll_14nm          798 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
pll_14nm          799 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
pll_14nm          807 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	DBG("DSI%d PLL save state %x %x", pll_14nm->id,
pll_14nm          815 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
pll_14nm          816 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
pll_14nm          817 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
pll_14nm          824 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 		DRM_DEV_ERROR(&pll_14nm->pdev->dev,
pll_14nm          831 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	DBG("DSI%d PLL restore state %x %x", pll_14nm->id,
pll_14nm          837 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
pll_14nm          838 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 		struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
pll_14nm          850 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
pll_14nm          851 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	void __iomem *base = pll_14nm->mmio;
pll_14nm          860 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 		pll_14nm->slave = pll_14nm_list[(pll_14nm->id + 1) % DSI_MAX];
pll_14nm          874 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->uc = uc;
pll_14nm          883 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
pll_14nm          884 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data;
pll_14nm          896 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
pll_14nm          897 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct platform_device *pdev = pll_14nm->pdev;
pll_14nm          898 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	int num_hws = pll_14nm->num_hws;
pll_14nm          903 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 		clk_hw_unregister(pll_14nm->hws[num_hws]);
pll_14nm          906 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
pll_14nm          913 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct device *dev = &pll_14nm->pdev->dev;
pll_14nm          927 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_postdiv->pll = pll_14nm;
pll_14nm          942 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
pll_14nm          952 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct device *dev = &pll_14nm->pdev->dev;
pll_14nm          953 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct clk_hw **hws = pll_14nm->hws;
pll_14nm          959 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	DBG("DSI%d", pll_14nm->id);
pll_14nm          967 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
pll_14nm          968 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->base.clk_hw.init = &vco_init;
pll_14nm          970 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	ret = clk_hw_register(dev, &pll_14nm->base.clk_hw);
pll_14nm          974 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	hws[num++] = &pll_14nm->base.clk_hw;
pll_14nm          976 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
pll_14nm          977 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id);
pll_14nm          980 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent,
pll_14nm          987 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id);
pll_14nm          988 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
pll_14nm          999 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
pll_14nm         1000 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
pll_14nm         1012 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id);
pll_14nm         1013 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
pll_14nm         1019 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4);
pll_14nm         1026 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->num_hws = num;
pll_14nm         1029 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->hw_data = hw_data;
pll_14nm         1032 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 				     pll_14nm->hw_data);
pll_14nm         1043 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	struct dsi_pll_14nm *pll_14nm;
pll_14nm         1050 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL);
pll_14nm         1051 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	if (!pll_14nm)
pll_14nm         1056 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->pdev = pdev;
pll_14nm         1057 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->id = id;
pll_14nm         1058 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm_list[id] = pll_14nm;
pll_14nm         1060 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
pll_14nm         1061 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
pll_14nm         1066 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
pll_14nm         1067 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	if (IS_ERR_OR_NULL(pll_14nm->mmio)) {
pll_14nm         1072 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	spin_lock_init(&pll_14nm->postdiv_lock);
pll_14nm         1074 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll = &pll_14nm->base;
pll_14nm         1084 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_14nm->vco_delay = 1;
pll_14nm         1089 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	ret = pll_14nm_register(pll_14nm);