pll_10nm 320 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll_10nm 322 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate, pll_10nm 325 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->vco_current_rate = rate; pll_10nm 326 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; pll_10nm 328 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_setup_config(pll_10nm); pll_10nm 330 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_calc_dec_frac(pll_10nm); pll_10nm 332 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_calc_ssc(pll_10nm); pll_10nm 334 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_commit(pll_10nm); pll_10nm 336 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_config_hzindep_reg(pll_10nm); pll_10nm 338 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_ssc_commit(pll_10nm); pll_10nm 407 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll_10nm 410 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_enable_pll_bias(pll_10nm); pll_10nm 411 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c if (pll_10nm->slave) pll_10nm 412 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_enable_pll_bias(pll_10nm->slave); pll_10nm 414 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0); pll_10nm 421 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, pll_10nm 431 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c rc = dsi_pll_10nm_lock_status(pll_10nm); pll_10nm 433 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pr_err("PLL(%d) lock failed\n", pll_10nm->id); pll_10nm 439 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_enable_global_clk(pll_10nm); pll_10nm 440 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c if (pll_10nm->slave) pll_10nm 441 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_enable_global_clk(pll_10nm->slave); pll_10nm 443 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, pll_10nm 445 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c if (pll_10nm->slave) pll_10nm 446 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->slave->phy_cmn_mmio + pll_10nm 462 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll_10nm 469 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_disable_global_clk(pll_10nm); pll_10nm 470 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); pll_10nm 471 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_disable_sub(pll_10nm); pll_10nm 472 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c if (pll_10nm->slave) { pll_10nm 473 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_disable_global_clk(pll_10nm->slave); pll_10nm 474 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_disable_sub(pll_10nm->slave); pll_10nm 485 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll_10nm 486 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll_10nm->mmio; pll_10nm 487 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c u64 ref_clk = pll_10nm->vco_ref_clk_rate; pll_10nm 516 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->id, (unsigned long)vco_rate, dec, frac); pll_10nm 535 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll_10nm 536 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; pll_10nm 537 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *phy_base = pll_10nm->phy_cmn_mmio; pll_10nm 540 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c cached->pll_out_div = pll_read(pll_10nm->mmio + pll_10nm 552 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->id, cached->pll_out_div, cached->bit_clk_div, pll_10nm 558 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll_10nm 559 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; pll_10nm 560 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *phy_base = pll_10nm->phy_cmn_mmio; pll_10nm 563 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); pll_10nm 566 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); pll_10nm 576 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c DBG("DSI PLL%d", pll_10nm->id); pll_10nm 584 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll_10nm 585 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll_10nm->phy_cmn_mmio; pll_10nm 588 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c DBG("DSI PLL%d", pll_10nm->id); pll_10nm 594 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->slave = pll_10nm_list[(pll_10nm->id + 1) % DSI_MAX]; pll_10nm 606 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->uc = uc; pll_10nm 615 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll_10nm 616 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data; pll_10nm 618 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c DBG("DSI PLL%d", pll_10nm->id); pll_10nm 630 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll_10nm 631 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct device *dev = &pll_10nm->pdev->dev; pll_10nm 633 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c DBG("DSI PLL%d", pll_10nm->id); pll_10nm 636 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw); pll_10nm 637 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); pll_10nm 638 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw); pll_10nm 639 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw); pll_10nm 640 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw); pll_10nm 641 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_divider(pll_10nm->bit_clk_hw); pll_10nm 642 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_divider(pll_10nm->out_div_clk_hw); pll_10nm 643 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister(&pll_10nm->base.clk_hw); pll_10nm 652 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) pll_10nm 663 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct device *dev = &pll_10nm->pdev->dev; pll_10nm 668 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c DBG("DSI%d", pll_10nm->id); pll_10nm 676 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id); pll_10nm 677 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->base.clk_hw.init = &vco_init; pll_10nm 679 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ret = clk_hw_register(dev, &pll_10nm->base.clk_hw); pll_10nm 683 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); pll_10nm 684 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id); pll_10nm 688 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->mmio + pll_10nm 696 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->out_div_clk_hw = hw; pll_10nm 698 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id); pll_10nm 699 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); pll_10nm 704 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->phy_cmn_mmio + pll_10nm 707 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c &pll_10nm->postdiv_lock); pll_10nm 713 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->bit_clk_hw = hw; pll_10nm 715 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id); pll_10nm 716 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); pll_10nm 726 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->byte_clk_hw = hw; pll_10nm 729 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); pll_10nm 730 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); pll_10nm 739 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->by_2_bit_clk_hw = hw; pll_10nm 741 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); pll_10nm 742 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); pll_10nm 751 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->post_out_div_clk_hw = hw; pll_10nm 753 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id); pll_10nm 754 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); pll_10nm 755 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); pll_10nm 756 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); pll_10nm 757 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); pll_10nm 762 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c }, 4, 0, pll_10nm->phy_cmn_mmio + pll_10nm 770 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->pclk_mux_hw = hw; pll_10nm 772 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id); pll_10nm 773 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id); pll_10nm 777 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 0, pll_10nm->phy_cmn_mmio + pll_10nm 780 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c &pll_10nm->postdiv_lock); pll_10nm 786 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->out_dsiclk_hw = hw; pll_10nm 790 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->hw_data = hw_data; pll_10nm 793 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->hw_data); pll_10nm 802 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw); pll_10nm 804 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_mux(pll_10nm->pclk_mux_hw); pll_10nm 806 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw); pll_10nm 808 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw); pll_10nm 810 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw); pll_10nm 812 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_divider(pll_10nm->bit_clk_hw); pll_10nm 814 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister_divider(pll_10nm->out_div_clk_hw); pll_10nm 816 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister(&pll_10nm->base.clk_hw); pll_10nm 823 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm; pll_10nm 827 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL); pll_10nm 828 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c if (!pll_10nm) pll_10nm 833 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->pdev = pdev; pll_10nm 834 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->id = id; pll_10nm 835 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm_list[id] = pll_10nm; pll_10nm 837 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); pll_10nm 838 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) { pll_10nm 843 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); pll_10nm 844 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c if (IS_ERR_OR_NULL(pll_10nm->mmio)) { pll_10nm 849 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c spin_lock_init(&pll_10nm->postdiv_lock); pll_10nm 851 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll = &pll_10nm->base; pll_10nm 860 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->vco_delay = 1; pll_10nm 862 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ret = pll_10nm_register(pll_10nm);