pll9             12813 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
pll9             1581 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	temp |= pll->state.hw_state.pll9;
pll9             1697 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
pll9             1698 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
pll9             1853 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
pll9             1933 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->pll9,
pll9              195 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;