pll8               82 drivers/clk/qcom/gcc-ipq806x.c static struct clk_pll pll8 = {
pll8             2758 drivers/clk/qcom/gcc-ipq806x.c 	[PLL8] = &pll8.clkr,
pll8               78 drivers/clk/qcom/gcc-mdm9615.c static struct clk_pll pll8 = {
pll8             1592 drivers/clk/qcom/gcc-mdm9615.c 	[PLL8] = &pll8.clkr,
pll8               27 drivers/clk/qcom/gcc-msm8660.c static struct clk_pll pll8 = {
pll8             2449 drivers/clk/qcom/gcc-msm8660.c 	[PLL8] = &pll8.clkr,
pll8               55 drivers/clk/qcom/gcc-msm8960.c static struct clk_pll pll8 = {
pll8             3144 drivers/clk/qcom/gcc-msm8960.c 	[PLL8] = &pll8.clkr,
pll8             3372 drivers/clk/qcom/gcc-msm8960.c 	[PLL8] = &pll8.clkr,
pll8             12812 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
pll8             1576 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	temp |= pll->state.hw_state.pll8;
pll8             1694 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
pll8             1695 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
pll8             1851 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	dpll_hw_state->pll8 = targ_cnt;
pll8             1932 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->pll8,
pll8              195 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;