pll1rate           19 arch/sh/kernel/cpu/sh2/clock-sh7619.c static const int pll1rate[] = {1,2};
pll1rate           25 arch/sh/kernel/cpu/sh2/clock-sh7619.c 	clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
pll1rate           44 arch/sh/kernel/cpu/sh2/clock-sh7619.c 	return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
pll1rate           18 arch/sh/kernel/cpu/sh2a/clock-sh7201.c static const int pll1rate[]={1,2,3,4,6,8};
pll1rate           27 arch/sh/kernel/cpu/sh2a/clock-sh7201.c 	       pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
pll1rate           21 arch/sh/kernel/cpu/sh2a/clock-sh7203.c static const int pll1rate[]={8,12,16,0};
pll1rate           29 arch/sh/kernel/cpu/sh2a/clock-sh7203.c 	clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
pll1rate           18 arch/sh/kernel/cpu/sh2a/clock-sh7206.c static const int pll1rate[]={1,2,3,4,6,8};
pll1rate           26 arch/sh/kernel/cpu/sh2a/clock-sh7206.c 	clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
pll1rate           45 arch/sh/kernel/cpu/sh2a/clock-sh7206.c 	return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
pll1rate           24 arch/sh/kernel/cpu/sh2a/clock-sh7264.c static const unsigned int pll1rate[] = {8, 12};
pll1rate           44 arch/sh/kernel/cpu/sh2a/clock-sh7264.c 	return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1];